This document presents the steps to setup an environment for using the EVAL-AD5272SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5272SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5272SDZ Evaluation Board.
The EVAL-AD5272SDZ evaluation board is a member of a growing number of boards available for the SDP. Designed to help customers evaluate performance or quickly prototype new AD5272 circuits and reduce design time, the EVAL-AD5272SDZ evaluation board can operate in single-supply and dual-supply mode and incorporates an internal power supply powered from the USB.
The AD5272 is a single-channel, 1024-position digital rheostat that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. The AD5272 ensure less than 1% end-to-end resistor tolerance error and offer 50-times programmable (50-TP) memory. The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. The AD5272 device wiper settings are controllable through the I2C-compatible digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5272 does not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer).
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-AD5272 reference project for Xilinx KC705 FPGA board.
|Displays all available commands.
|Makes a software reset of the device.
| Writes to the RDAC register. Accepted values:
0 .. 1024 (0 .. 255 for AD5274) - the value written to RDAC.
|Displays the last written value in RDAC register.
|Stores the RDAC setting to 50-TP.
| Displays the contents of the selected 50-TP register. Accepted values:
0 .. 50 - selected 50-TP register.
|Displays the address of the last programmed 50-TP register.
| Turns on/off the device. Accepted values:
1 - normal mode.(default)
0 - shutdown mode.
|Displays the power status of the device.
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: