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resources:fpga:xilinx:interposer:ad5252 [06 Apr 2012 15:44] – [More information] Andrei Cozmaresources:fpga:xilinx:interposer:ad5252 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5252|EVAL-AD5252SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5252SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5252|EVAL-AD5252SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5252SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:ad5252.jpg?400 }} {{ :resources:fpga:xilinx:interposer:ad5252.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5252SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5252SDZ** Evaluation Board.
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   * [[adi>AD5252|AD5252 Product Info]] - pricing, samples, datasheet   * [[adi>AD5252|AD5252 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-274.pdf|EVAL-AD5252SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-274.pdf|EVAL-AD5252SDZ evaluation board user guide]]
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] +  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD5252** evaluation board   * **EVAL-AD5252** evaluation board
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.
  
 ===== Downloads ===== ===== Downloads =====
 +<WRAP round download 80%>
 +\\
 +  * **AD5252 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/potentiometer/ad525x
 +  * **AD5252 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD525x
 +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
 +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
 +\\
 +</WRAP>
  
-  * {{:resources:fpga:xilinx:interposer:ad5252_evalboard.zip|Reference Design Files}}+===== Hardware setup ===== 
 +<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-The following table presents a short description the reference design archive contents.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-^ **Folder** ^ **Description** ^ +===== Reference Project Overview =====
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. |+
  
-====== Run the Demonstration Project ======+The following commands were implemented in this version of EVAL-AD5252 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **rdac=** | Load the wiper register with a give value. Accepted values:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register.\\ value:\\ 0 .. 255 - value to be written in register. | 
 +| **rdac?** | Read back the value of the wiper register. Accepted values:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **reset!** | Reset all wiper register to its stored values | 
 +| **restore=** | Restore the specified wiper register setting form the memory. Accepted value:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **save=** | Save the given wiper register settings to the memory. Accepted value:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **writemem=** | Write to one of the user memory address. Accepted value:\\ address: a value between 0x2 and 0xE.\\ data: a value between 0 and 255.|   
 +| **readmem=** | Read data from the EEMEM memory. Accepted value:\\  address: a value between 0x2 and 0xE. | 
 +| **decrdacdb=** | Decrement a given wiper register by 6dB. Accepted value:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **decrdacdball!** | Decrement all wiper register by 6dB. | 
 +| **decrdac=** | Decrement a given wiper register by one. Accepted value:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **decrdacall!** | Decrement all wiper register by one. | 
 +| **incrdacdb=** | Increment a given wiper register by 6dB. Accepted value:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **incrdacdball!** | Increment all wiper register by 6dB. | 
 +| **incrdac=** | Increment a given wiper register by one. Accepted value:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | 
 +| **incrdacall!** | Increment all wiper register by one. | 
 +| **setwp=** | Set the state of the Write Protect (WP) pin. Accepted value:\\ desired state:\\ 0 - inactive\\ 1 - active | 
 +| **getwp?** | Return the current value of the Write Protect (WP) pin | 
 +| **sethwreset=** | Set the state of the Hardware Override Preset (PR) pin. Accepted value:\\ 0 - inactive\\ 1 - active | 
 +| **gethwreset?** | Return the current value of the Hardware Override Preset (PR) pin | 
 +| **tolerance=** | Read one of the Tolerance register. Accepted value:\\ 0x0 .. 0x3 - virtual address of the tolerance register | 
  
-{{page>ucprobe_common}}+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-===== Demonstration Project User Interface =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5252SDZ** evaluation board.+===== Software Project Setup ===== 
 +{{page>import_workspace}}
  
-{{ :resources:fpga:altera:bemicro:ad5252_interface.png?700 }} 
- 
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. 
- 
-**Section B** is used to update the RDAC registers. The RDAC registers can be updated by selecting a desirable value on the slider and clicking **//Load RDACx//**. 
- 
-**Section C** is used to read/write data from/into memory block. The location can be chosen from the EEMEM slider. Each location can be read, or updated with the value from the second slider. 
- 
-**Section D** is used to display the stored tolerance of each internal resistor. 
- 
-**Section E** is used to send two bytes to the AD5252 circuit. A customized I2C data-word can be sent by manually switching the buttons from 0 to 1 or from 1 to 0 as desired and then clicking **//Send Data//**. 
- 
-**Section F** is used to enable or disable the AD5252 WP pin. 
- 
-**Section G** is used to send the AD5252 quick commands directly to the AD5252. 
- 
- 
-===== Troubleshooting ===== 
- 
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: 
-  * Check that the evaluation board is powered as instructed in the board's user guide. 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. 
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. 
  
 ====== More information ====== ====== More information ======
   * [[resources:tools-software:linux-drivers:misc:dpot|AD5252 Digital Potentiometer Linux Driver]]   * [[resources:tools-software:linux-drivers:misc:dpot|AD5252 Digital Potentiometer Linux Driver]]
-  * [[ez>community/fpga|ask questions about the FPGA reference design]]+{{page>ez_common}}
resources/fpga/xilinx/interposer/ad5252.1333719860.txt.gz · Last modified: 06 Apr 2012 15:44 (external edit)

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