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resources:fpga:xilinx:interposer:ad5172 [28 Sep 2012 11:28] Adrian Costina Added common section for describing the evaluation setup and System Demonstration Platform |
resources:fpga:xilinx:interposer:ad5172 [09 Jan 2021 00:48] Robin Getz user interwiki links |
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| ====== Overview ====== | ====== Overview ====== | ||
| - | This document presents the steps to setup an environment for using the **[[adi>AD5172|EVAL-AD5172SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5172SDZ Evaluation Board with the Xilinx KC705 board. | + | This document presents the steps to setup an environment for using the **[[adi>AD5172|EVAL-AD5172SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5172SDZ Evaluation Board with the Xilinx KC705 board. |
| {{ :resources:fpga:xilinx:interposer:ad5172.jpg?400 }} | {{ :resources:fpga:xilinx:interposer:ad5172.jpg?400 }} | ||
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| * [[adi>AD5172|AD5172 Product Info]] - pricing, samples, datasheet | * [[adi>AD5172|AD5172 Product Info]] - pricing, samples, datasheet | ||
| * [[adi>/static/imported-files/user_guides/UG-243.pdf|EVAL-AD5172SDZ evaluation board user guide]] | * [[adi>/static/imported-files/user_guides/UG-243.pdf|EVAL-AD5172SDZ evaluation board user guide]] | ||
| - | * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] | + | * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] |
| - | * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] | + | |
| ====== Getting Started ====== | ====== Getting Started ====== | ||
| Line 37: | Line 36: | ||
| ===== Required Hardware ===== | ===== Required Hardware ===== | ||
| - | * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] | + | * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] |
| * FMC-SDP adapter board | * FMC-SDP adapter board | ||
| * **EVAL-AD5172** evaluation board | * **EVAL-AD5172** evaluation board | ||
| Line 43: | Line 42: | ||
| ===== Required Software ===== | ===== Required Software ===== | ||
| - | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
| - | * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool | + | * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. |
| ===== Downloads ===== | ===== Downloads ===== | ||
| + | <WRAP round download 80%> | ||
| + | \\ | ||
| + | * **AD5172 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5172 | ||
| + | * **AD5172 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5172 | ||
| + | * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common | ||
| + | * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 | ||
| + | \\ | ||
| + | </WRAP> | ||
| - | * {{:resources:fpga:xilinx:interposer:ad5172_evalboard.zip|Reference Design Files}} | + | ===== Hardware setup ===== |
| - | The following table presents a short description the reference design archive contents. | + | <WRAP round important 80%> |
| + | \\ | ||
| + | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. | ||
| + | </WRAP> | ||
| - | ^ **Folder** ^ **Description** ^ | + | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. |
| - | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | * Connect the JTAG and UART cables to the KC705 and power up the FPGA board. |
| - | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | |
| - | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | + | |
| - | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
| - | ====== Run the Demonstration Project ====== | + | ===== Reference Project Overview ===== |
| + | The following commands were implemented in this version of EVAL-AD5172 reference project for Xilinx KC705 FPGA board. | ||
| + | ^ Command ^ Description ^ | ||
| + | | **help?** | Displays all available commands. | | ||
| + | | **rdac=** | Load the wiper register with a give value. Accepted values:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register.\\ value:\\ 0 .. 255 - value to be written in register. | | ||
| + | | **rdac?** | Read back the value of the wiper register. Accepted values:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | | ||
| + | | **wbuf1?** | Read back the value of the Wiper Buffer in voltage. (VDD=3.2V) | | ||
| + | | **shutdown=** | Shutdown connects wiper to B terminal and open circuits the A terminal. channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | | ||
| + | | **shutdown?** | Notify about the state of the selected RDAC. channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | | ||
| - | {{page>ucprobe_common}} | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
| - | ===== Demonstration Project User Interface ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
| + | {{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }} | ||
| - | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5172SDZ** evaluation board. | + | ===== Software Project Setup ===== |
| - | + | {{page>import_workspace}} | |
| - | {{ :resources:fpga:altera:bemicro:ad5172interface.png?700 }} | + | |
| - | + | ||
| - | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. | + | |
| - | + | ||
| - | **Section B** is used to update the RDAC registers, to switch the device to shutdown mode and to program the wiper permanently.The RDAC registers can be updated by selecting a desirable value on the slider and clicking **//Load RDACx//**. | + | |
| - | * **//Shutdown//**: When it is pressed, connects wiper to B terminal and open circuits the A terminal. It does not change the contents of the wiper register. When it is released, the previous latch settings put the wiper in the same resistance setting prior to shutdown. | + | |
| - | * **//Program//**: When it is pressed, programs the wiper permanently. The **//Fuse Status//** numeric box shows the status of the device's fuse and can have the followin values: 0 - ready, 2 - error, 3 - success. | + | |
| - | + | ||
| - | **Section C** is used to send one or two bytes to the AD5172 circuit. A customized I2C data-word can be sent by manually switching the buttons from 0 to 1 or from 1 to 0 as desired and then toggling the **//Send Data//** switch. The number of bytes to send can be selected by switching the **//Bytes to Send//** switch to 1 or 2. | + | |
| - | + | ||
| - | ===== Troubleshooting ===== | + | |
| - | + | ||
| - | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
| - | * Check that the evaluation board is powered as instructed in the board's user guide. | + | |
| - | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. | + | |
| - | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
| ====== More information ====== | ====== More information ====== | ||
| * [[resources:tools-software:linux-drivers:misc:dpot|AD5172 Digital Potentiometer Linux Driver]] | * [[resources:tools-software:linux-drivers:misc:dpot|AD5172 Digital Potentiometer Linux Driver]] | ||
| {{page>ez_common}} | {{page>ez_common}} | ||
resources/fpga/xilinx/interposer/ad5172.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz