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resources:fpga:xilinx:interposer:ad5162 [28 May 2012 15:50] – Approved Alexandru.Tofan | resources:fpga:xilinx:interposer:ad5162 [09 Oct 2013 16:46] – Correct typos Istvan Csomortani | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
- | For component evaluation and performance purposes, as opposed to quick prototyping, | + | {{page>common_sdp}} |
- | * a controller board, like the **[[resources/ | + | |
- | * a compatible Analog Devices SDP [[adi>sdp# | + | |
- | * corresponding PC software | + | |
- | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. | + | |
Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5162SDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5162SDZ** Evaluation Board. | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
===== Downloads ===== | ===== Downloads ===== | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | * **AD5162 Driver:** https:// | ||
+ | * **AD5162 Commands:** https:// | ||
+ | * **Xilinx Boards Common Drivers:** https:// | ||
+ | * **EDK KC705 Reference project:** https:// | ||
+ | \\ | ||
+ | </ | ||
- | * {{: | + | ===== Hardware setup ===== |
- | The following table presents a short description | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | ^ **Folder** ^ **Description** ^ | + | |
- | | Bit | Contains | + | * Connect |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | |
- | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | + | |
- | | uCProbeInterface | Contains | + | |
- | ====== Run the Demonstration | + | ===== Reference |
+ | The following commands were implemented in this version of EVAL-AD5162 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **rdac=** | Load the wiper register with a give value. Accepted values:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register.\\ value:\\ 0 .. 255 - value to be written in register. | | ||
+ | | **rdac?** | Read back the value of the wiper register. Accepted values:\\ channel:\\ 0 - select RDAC 1 wiper register.\\ 1 - select RDAC 2 wiper register. | | ||
+ | | **wbuf1?** | Read back the value of the Wiper Buffer in voltage. (VDD=3.2V) | | ||
+ | | **shutdown=** | Shutdown connects wiper to B terminal and open circuits the A terminal. **This command is not supported by this device.** | | ||
+ | | **shutdown? | ||
- | {{page> | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
- | ===== Demonstration Project User Interface ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5162SDZ** evaluation board. | + | ===== Software Project Setup ===== |
- | + | {{page> | |
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | **Section B** is used to configure the values set on channels 1 and 2 and also displays the voltage on the W1_BUF pin. | + | |
- | It is assumed that jumper A20 is in position AC+DC, A21 in position GND, A24 in position +3.3V and A25 in position GND. | + | |
- | + | ||
- | ===== Troubleshooting | + | |
- | + | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
- | * Check that the evaluation board is powered as instructed in the board' | + | |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
{{page> | {{page> |