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resources:fpga:xilinx:interposer:ad5110 [19 Mar 2012 15:55] – Approved Andrei Cozma | resources:fpga:xilinx:interposer:ad5110 [09 Jan 2021 00:39] (current) – user interwiki links Robin Getz | ||
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* [[adi> | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
===== Evaluation Boards ===== | ===== Evaluation Boards ===== | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
- | For component evaluation and performance purposes, as opposed to quick prototyping, | + | {{page>common_sdp}} |
- | * a controller board, like the **[[resources/ | + | |
- | * a compatible Analog Devices SDP [[adi>sdp# | + | |
- | * corresponding PC software | + | |
- | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. | + | |
Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5110SDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5110SDZ** Evaluation Board. | ||
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===== More information ===== | ===== More information ===== | ||
* [[adi> | * [[adi> | ||
- | * [[adi>/ | + | * [[adi>/ |
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
- | * **EVAL-AD5110** evaluation board | + | * **EVAL-AD5110SDZ** evaluation board |
===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5110 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5110 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5110 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5110SDZ** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | **Section B** allows the user to write data to the internal RDAC Register. The value can be set using the slider provided, and the write operation will take place after clicking the Write RDAC button. | + | |
- | + | ||
- | **Section C** allows the user to read the value programmed in the RDAC Register by pressing the Read RDAC button. | + | |
- | **Section D** is used to read the value of RDAC programmed in the internal EEPROM. | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage | ||
+ | </ | ||
- | **Section E** displays | + | |
+ | | ||
- | **Section F** is used to shutdown | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD5110 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Makes a software reset of the device. | | ||
+ | | **rdac=** | Writes | ||
+ | | **rdac?** | Displays the last written value in RDAC register. | | ||
+ | | **rdacToEeprom!** | Writes the content of RDAC register to EEPROM. | | ||
+ | | **wiper?** | Displays the wiper resistance from EEPROM. | | ||
+ | | **tolerance? | ||
+ | | **power=** | Turns on/ | ||
+ | | **power?** | Displays the power status of the device. | | ||
- | **Section G** is used to perform a Software Reset (loads the RDAC Register with the value programmed in the EEPROM). | ||
- | **Section H** allows the user to save the current value of the RDAC Register into the internal EEPROM. | + | Commands can be executed using a serial terminal connected |
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
- | * [[ez>community/ | + | {{page>ez_common}} |