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resources:fpga:xilinx:fmc:fmc-imageon [29 Sep 2017 09:34]
AdrianC [Supported Carriers] Added FMC slot specification
resources:fpga:xilinx:fmc:fmc-imageon [20 Mar 2018 16:42] (current)
AdrianC Removed ZC706/ML605 projects
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 ====== FMC-IMAGEON Xilinx Reference Design ====== ====== FMC-IMAGEON Xilinx Reference Design ======
    
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 ===== Supported Carriers ===== ===== Supported Carriers =====
  
-  * [[xilinx>​ZC706]] LPC Slot 
   * [[http://​zedboard.org/​product/​zedboard|ZedBoard]] ​   * [[http://​zedboard.org/​product/​zedboard|ZedBoard]] ​
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   * We upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://​github.com/​analogdevicesinc/​hdl/​tree/​master | git repository ]].    * We upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://​github.com/​analogdevicesinc/​hdl/​tree/​master | git repository ]]. 
   * A UART terminal (Tera Term/​Hyperterminal),​ Baud rate 57600.   * A UART terminal (Tera Term/​Hyperterminal),​ Baud rate 57600.
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 ===== Using the reference design ===== ===== Using the reference design =====
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 |{{.:​cf_adv7x11_bd.jpg?​200|Block Diagram}} | |{{.:​cf_adv7x11_bd.jpg?​200|Block Diagram}} |
  
-The reference design consists of two independent ​pcore modules.+The reference design consists of two independent ​IP modules.
  
-The video part consists of a Xilinx VDMA interface and the ADV7511/​ADV7611 video interface. The video interface consists of a 16bit YCbCr 422 with embedded ​synchorinzation ​signals.+The video part consists of a Xilinx VDMA interface and the ADV7511/​ADV7611 video interface. The video interface consists of a 16bit YCbCr 422 with embedded ​synchronization ​signals.
  
 ==== Video Transmit (VDMA to HDMI) ==== ==== Video Transmit (VDMA to HDMI) ====
  
-In the transmit direction, the VDMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.+In the transmit direction, the VDMA streams frame data to this core. The internal buffers of this IP are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.
  
 The reference design defaults to the 1080p video mode. Users may change the video settings by programming the video size registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally. The reference design defaults to the 1080p video mode. Users may change the video settings by programming the video size registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally.
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 ==== Video Receive (HDMI to VDMA) ==== ==== Video Receive (HDMI to VDMA) ====
  
-In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to VDMA. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611.+In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to VDMA. The internal buffers of this IP are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611.
  
 The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to VDMA to avoid possible lock up conditions in the VDMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the VDMA interface as it is. The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to VDMA to avoid possible lock up conditions in the VDMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the VDMA interface as it is.
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 ==== Registers ==== ==== Registers ====
  
-Please refer to the regmap.txt file inside the pcores.+{{page>:​resources:​fpga:​docs:​hdl:​regmap##​Base (common ​to all cores)&​nofooter&​noeditbtn}} 
 + 
 +{{page>:​resources:​fpga:​docs:​hdl:​regmap##​ HDMI Transmit (axi_hdmi_tx)&​nofooter&​noeditbtn}} 
 + 
 +{{page>:​resources:​fpga:​docs:​hdl:​regmap##HDMI Receive (axi_hdmi_rx) &​nofooter&​noeditbtn}}
  
 ==== Audio Registers (axi_spdif_tx) ==== ==== Audio Registers (axi_spdif_tx) ====
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 |      | 0    | 0       | audio             | Data format is non-audio (0x1) or audio (0x0) (RO). | |      | 0    | 0       | audio             | Data format is non-audio (0x1) or audio (0x0) (RO). |
 | 1. For AXI-Lite byte addresses, multiply by 4. ||||| | 1. For AXI-Lite byte addresses, multiply by 4. |||||
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 ===== Using the ADV7511 Transmitter Library ===== ===== Using the ADV7511 Transmitter Library =====
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   * In the //Import Projects// window select the //​**SDK_Workspace**//​ folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //​Projects//​ list. Press //Finish// to finalize the import process.   * In the //Import Projects// window select the //​**SDK_Workspace**//​ folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //​Projects//​ list. Press //Finish// to finalize the import process.
 {{:​resources:​fpga:​xilinx:​fmc:​fmc-imageon:​projects_import.png?​300|Projects Import}} {{:​resources:​fpga:​xilinx:​fmc:​fmc-imageon:​projects_import.png?​300|Projects Import}}
-  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display ​the the result of the build. If the build is not done automatically select the //​**Project->​Build Automatically**//​ menu option.+  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //​**Project->​Build Automatically**//​ menu option.
 {{:​resources:​fpga:​xilinx:​fmc:​fmc-imageon:​project_explorer.png?​300|Project Explorer}} {{:​resources:​fpga:​xilinx:​fmc:​fmc-imageon:​project_explorer.png?​300|Project Explorer}}
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 ===== Downloads ===== ===== Downloads =====
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 **HDL Reference Designs:** **HDL Reference Designs:**
  
-<WRAP round download 80%> +{{page>resources/fpga/​docs/​hdl/​downloads_insert#​fmcimageong}}
-  * **ML605: ** {{:resources:fpga:​xilinx:​fmc:​cf_adv7x11_edk_14_4_2013_03_14.tar.gz}} +
-  * **Zed: ** {{:​resources:​fpga:​xilinx:​fmc:​cf_imageon_zed_edk_14_4_2013_03_14.tar.gz}} +
-  * **ADV7511 Transmitter Library Demo: ** {{:​resources:​fpga:​xilinx:​fmc:​fmc-imageon:​adv7511_transmitter_library_demo.zip}} +
-</​WRAP>​+
  
 **ADV7511 Transmitter Library Demo Software** **ADV7511 Transmitter Library Demo Software**
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 </​WRAP>​ </​WRAP>​
  
-<WRAP round help 80%> +{{page>resources/fpga/docs/hdl/downloads_insert#​help_support}}
-  * Questions? [[https://​ez.analog.com/​community/fpga|Ask Help & Support]]. +
-</WRAP> +
- +
- +
-===== Tar file contents ===== +
- +
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://​www.xilinx.com/​support/​documentation/​dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details. +
- +
-| license.txt | ADI license & copyright information. | +
-| system.mhs ​ | MHS file. | +
-| system.xmp ​ | XMP file (use this file to build the reference design). | +
-| data/       | UCF file and/or DDR MIG project files. | +
-docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). | +
-| sw/         | Software (Xilinx SDK) & bit file(s). | +
-| cf_lib/​edk/​pcores    | Reference design core file(s) (Xilinx EDK). | +
  
resources/fpga/xilinx/fmc/fmc-imageon.txt · Last modified: 20 Mar 2018 16:42 by AdrianC