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resources:fpga:xilinx:fmc:ad9739a [11 Nov 2016 11:08] – [Supported Devices] increase size for board picture Lucian Sin | resources:fpga:xilinx:fmc:ad9739a [12 Feb 2021 11:55] (current) – [Quick Start Guide] -update video tutorial link Dan Nechita | ||
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===== Supported Carriers ===== | ===== Supported Carriers ===== | ||
- | * [[xilinx> | + | * [[xilinx> |
- | * [[xilinx> | + | * [[xilinx> |
- | * [[xilinx> | + | * [[xilinx> |
- | * [[xilinx> | + | * [[xilinx> |
+ | * [[xilinx> | ||
===== Quick Start Guide ===== | ===== Quick Start Guide ===== | ||
- | The reference design has been tested on ML605(Virtex-6), | + | The reference design has been tested on ML605(Virtex-6), |
- | {{analogTV> | + | A video tutorial is available: |
==== Required Hardware ==== | ==== Required Hardware ==== | ||
* ML605/ | * ML605/ | ||
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* Xilinx ISE Design Suite 14.4 | * Xilinx ISE Design Suite 14.4 | ||
* A UART terminal (Tera Term/ | * A UART terminal (Tera Term/ | ||
- | * [[http:// | + | * [[/ |
==== Running Demo (SDK) Program ==== | ==== Running Demo (SDK) Program ==== | ||
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The reference design consists of two functional modules, a DDS/LVDS interface and a SPI interface. It is part of an AXI based microblaze system as shown in the block diagram below. It is designed to support linux running on microblaze. All other peripherals are available from Xilinx as IP cores. | The reference design consists of two functional modules, a DDS/LVDS interface and a SPI interface. It is part of an AXI based microblaze system as shown in the block diagram below. It is designed to support linux running on microblaze. All other peripherals are available from Xilinx as IP cores. | ||
- | {{: | + | === Xilinx block diagram === |
+ | {{: | ||
+ | === AD9739A FMC Card block diagram === | ||
+ | {{: | ||
The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The core generates 6 samples at every fDAC/3 clock cycles for each port of AD9739A. | The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The core generates 6 samples at every fDAC/3 clock cycles for each port of AD9739A. | ||
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**no-OS Software:** | **no-OS Software:** | ||
<WRAP round download 80%> | <WRAP round download 80%> | ||
- | * **AD9739A Driver: | + | * **AD9739A Driver: |
- | * **ADF4350 Driver: | + | * **ADF4350 Driver: |
* **AD9739A-FMC-EBZ Reference Design: ** https:// | * **AD9739A-FMC-EBZ Reference Design: ** https:// | ||
- | * **Xilinx Platform Drivers: | + | * **Xilinx Platform Drivers: |
* **DAC Core Driver: | * **DAC Core Driver: | ||
</ | </ | ||
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<WRAP round help 80%> | <WRAP round help 80%> | ||
\\ | \\ | ||
- | * Questions? [[https://ez.analog.com/ | + | * Questions? [[ez>community/ |
\\ | \\ | ||
</ | </ | ||
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<WRAP round help 80%> | <WRAP round help 80%> | ||
- | * [[http:// | + | * [[adi>en/ |
* [[http:// | * [[http:// | ||
* [[ez> | * [[ez> | ||
* [[ez> | * [[ez> | ||
</ | </ |