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resources:fpga:xilinx:fmc:ad9467 [20 Apr 2020 13:32]
Umesh Jayamohan updated 9467fmc01c.zip file to remove specific email address
resources:fpga:xilinx:fmc:ad9467 [09 Jan 2021 00:39] (current)
Robin Getz user interwiki links
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 ===== Evaluation Board Hardware ===== ===== Evaluation Board Hardware =====
  
-To find out more information about the [[http://​www.analog.com/​en/​design-center/​evaluation-hardware-and-software/​evaluation-boards-kits/​EVAL-AD9467.html#​eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[http://​www.analog.com/​media/​en/​technical-documentation/​user-guides/​UG-200.pdf|UG200]])+To find out more information about the [[adi>en/​design-center/​evaluation-hardware-and-software/​evaluation-boards-kits/​EVAL-AD9467.html#​eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[adi>media/​en/​technical-documentation/​user-guides/​UG-200.pdf|UG200]])
  
 {{:​resources:​fpga:​xilinx:​fmc:​ad9467_fmc.jpg?​300|}} {{:​resources:​fpga:​xilinx:​fmc:​ad9467_fmc.jpg?​300|}}
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 The evaluation board can be set up to be clocked from the **crystal oscillator**,​ Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running. ​ The evaluation board can be set up to be clocked from the **crystal oscillator**,​ Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running. ​
  
-A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[http://​www.analog.com/​media/​en/​technical-documentation/​data-sheets/​AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.+A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi>media/​en/​technical-documentation/​data-sheets/​AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.
  
 <WRAP round important 100%> <WRAP round important 100%>
 \\ \\
-Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found at the [[http://​wiki.analog.com/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Download]] section.+Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found at the [[/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Download]] section.
 </​WRAP>​ </​WRAP>​
  
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 ==== Required Software ==== ==== Required Software ====
  
-  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our HDL [[https://​wiki.analog.com/​resources/​fpga/​docs/​releases | release page]].  ​+  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our HDL [[/​resources/​fpga/​docs/​releases | release page]].  ​
   * A UART terminal (Tera Term/​Hyperterminal),​ baud rate 115200.   * A UART terminal (Tera Term/​Hyperterminal),​ baud rate 115200.
  
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 <WRAP round info 100%> <WRAP round info 100%>
-Instruction about how to build the HDL design and generate a bit stream can be found [[https://​wiki.analog.com/​resources/​fpga/​docs/​build | here]]. ​+Instruction about how to build the HDL design and generate a bit stream can be found [[/​resources/​fpga/​docs/​build | here]]. ​
 </​WRAP>​ </​WRAP>​
  
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   * Capture data from the AD9467 using DMA transfers   * Capture data from the AD9467 using DMA transfers
  
-The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[http://​wiki.analog.com/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Downloads]] section.+The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Downloads]] section.
  
 ==== AD9467 Software Driver ==== ==== AD9467 Software Driver ====
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 <WRAP round info 100%> <WRAP round info 100%>
-Instruction about how to create a software application can be found [[http://​wiki.analog.com/​resources/​fpga/​xilinx/​software_setup|here]]. ​+Instruction about how to create a software application can be found [[/​resources/​fpga/​xilinx/​software_setup|here]]. ​
 </​WRAP>​ </​WRAP>​
  
-The exact location of the no-OS source files can be found in the [[http://​wiki.analog.com/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Download]] section. ​+The exact location of the no-OS source files can be found in the [[/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Download]] section. ​
   ​   ​
 ===== Downloads ===== ===== Downloads =====
resources/fpga/xilinx/fmc/ad9467.1587382372.txt.gz · Last modified: 20 Apr 2020 13:32 by Umesh Jayamohan