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resources:fpga:xilinx:fmc:ad9467 [27 Feb 2015 10:00]
Istvan Csomortani [Required Hardware] Update for Vivado
resources:fpga:xilinx:fmc:ad9467 [09 Jan 2021 00:39] (current)
Robin Getz user interwiki links
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 The [[adi>​AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the [[adi>​AD9517-4]] clock chip and/or setting up the ADL5565 differential amplifier respectively. ​ The [[adi>​AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the [[adi>​AD9517-4]] clock chip and/or setting up the ADL5565 differential amplifier respectively. ​
  
-===== Supported Devices ​=====+===== Evaluation Board Hardware ​===== 
 + 
 +To find out more information about the [[adi>​en/​design-center/​evaluation-hardware-and-software/​evaluation-boards-kits/​EVAL-AD9467.html#​eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[adi>​media/​en/​technical-documentation/​user-guides/​UG-200.pdf|UG200]])
  
-  * [[adi>​EVAL-AD9467| AD9467-FMC ]] 
 {{:​resources:​fpga:​xilinx:​fmc:​ad9467_fmc.jpg?​300|}} {{:​resources:​fpga:​xilinx:​fmc:​ad9467_fmc.jpg?​300|}}
  
-===== Supported Carriers =====+==== Clock Selection ​==== 
 + 
 +The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467.  
 + 
 +The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. 
 + 
 +The evaluation board can be set up to be clocked from the **crystal oscillator**,​ Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running. ​
  
-^ Board     ^ XPS     ^ Vivado ​    ^ +**differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi>media/en/technical-documentation/​data-sheets/​AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.
-| [[xilinx>​ML605]] |  ​**DISCONTINUED**  ​| ​   | +
-[[xilinx>KC705]] |  **DISCONTINUED** ​ |  **x**  | +
-| [[xilinx>​VC707]] |  **DISCONTINUED** ​ |    | +
-| [[http://www.zedboard.orgZed +
-Board]] |  **DISCONTINUED** ​ |  **x**  |  ​+
  
-<WRAP round important ​80%>+<WRAP round important ​100%>
 \\ \\
-The XPS projects remain ​on this website only for legacy purposes. The support for them has been discontinued+Please make sure you have removed or inserted the corresponding components ​on the board to select the desired clock path. The schematic of the board can be found at the [[/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Download]] section.
 </​WRAP>​ </​WRAP>​
  
-===== Quick Start Guide =====+===== Supported Carriers ​=====
  
-The reference design has been tested with ML605, ​KC705, VC707 and ZedThe notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have.+  * [[xilinx>​KC705]] LPC Slot 
 +  * [[http://​www.zedboard.org| ZedBoard]]
  
-==== Required Hardware ==== +==== Other Required Hardware ====
-  * KC705/Zed board +
-  * AD9467-FMC-EBZ board +
-  * Signal generator (for data) +
-  * Signal generator (for clock) (optional)+
  
 +  * Signal synthesizer (for data and/or clock input).
  
 ==== Required Software ==== ==== Required Software ====
  
-  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/​tree/​master ​git repository ​]].  ​+  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our HDL [[/resources/fpga/docs/releases ​release page]].  ​
   * A UART terminal (Tera Term/​Hyperterminal),​ baud rate 115200.   * A UART terminal (Tera Term/​Hyperterminal),​ baud rate 115200.
  
-==== Running Demo (SDK) Program ​==== +===== Using the HDL reference design =====
-To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. ** The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). ** However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a clock source to the CLKIN SMA connector and a signal source to the AIN SMA connector of the FMC card. After the hardware setup, turn the power on to the ML605.+
  
-{{:resources:fpga:​xilinx:​fmc:​cf_ad9467_setup.jpg?​200|Hardware setup}}+<WRAP round info 100%> 
 +Instruction about how to build the HDL design and generate a bit stream can be found [[/resources/fpga/​docs/​build ​here]].  
 +</​WRAP>​
  
-Run the **//​download.bat//​** script located in the "//​SDK/​SDK_Workspace/​bin//"​ folder provided within the HDL Reference Design. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR. +==== Functional description ====
  
-**Note:​** ​The //​download.bat//​ script assumes that the //Xilinx ISE Design Suite 14.4// ​is installed at this path:  ​//​C:/​Xilinx/​14.4//. If the installation path on your computer ​is different please modify the script accordingly.+The reference design ​is built on a ARM/Microblaze based system tailored for LinuxA functional block diagram of the design ​is given below.
  
-If programming was successful, you should be seeing messages appear on the terminal as shown in figure below+=== Xilinx block diagram === 
 +{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​ad9467_fmc.svg?​500|Xilinx HDL Block Diagram}}
  
-{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​ad9467_test.png?200|Terminal}}+=== AD9467 FMC Card block diagram === 
 +{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​ad9467_fmc_card.svg?400|Xilinx HDL Block Diagram}}
  
-The reference design contains an example on how to: 
-  * Initialize the AD9467 evaluation board 
-  * Initialize the AD9467 HDL core 
-  * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467 
-  * Capture data from the AD9467 using DMA transfers 
  
-After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "//​Chipscope//"​ folder provided in the HDL Reference Design. These are the steps than need to be followed to view the ADC data in Chipscope:​ +Through an SPI interface, the software ​can access ​the AD9467/AD9517-4 registers, given the possibility ​to initialize and configure ​the ADC and/or clock chip.  ​
-  * open Chipscope ​and press the **//Open Cable/​Search JTAG Chain//** button (the leftmost button located under the File menu) +
-  * open the //​Chipscope/​AD9467.cpj// project  +
-  * start the data capture +
-This is how the output of the ADC looks like. +
- +
-{{:​resources:​fpga:​xilinx:​fmc:​cf_ad9467_chipscope.jpg?​200|Chipscope Busplot}} +
-===== Using the HDL reference design ===== +
- +
-==== Functional description ==== +
- +
-The reference design is built on a Microblaze based system parameterized for Linux. A functional block diagram of the design is given below. +
- +
-{{:​resources:​fpga:​xilinx:​fmc:​cf_ad9467_bd.jpg?​400|block diagram}} +
- +
-The reference design consists of three functional modules, a LVDS interface, a PN9/​PN23/​PAT monitor and a DMA interface. ​+
  
 The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
- 
- 
-==== Registers ==== 
- 
-Refer to the **//​regmap.txt//​** file inside the pcores directory. 
  
 ==== Good To Know ==== ==== Good To Know ====
Line 88: Line 66:
  
 The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the "​capture select"​ bit (register 0x0a, bit 0). The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the "​capture select"​ bit (register 0x0a, bit 0).
- 
-==== Clock Selection ==== 
- 
-The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. ​ 
- 
-  * External passive clock (default): A SMA connector is provided for an external clock source. 
-  * Optional active clock path or using the AD9517 : You may use either the PECL (OUT3) or the LVDS (OUT5) outputs. The optional oscillator may be used as a clock source for the AD9517 REF or CLK inputs. 
-  * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active (AD9517) path. 
- 
-**Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path.** 
  
 ===== Using the Software Reference Design ===== ===== Using the Software Reference Design =====
Line 107: Line 75:
   * Capture data from the AD9467 using DMA transfers   * Capture data from the AD9467 using DMA transfers
  
-The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the **Downloads** section.+The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Downloads]] section. 
 ==== AD9467 Software Driver ==== ==== AD9467 Software Driver ====
  
Line 139: Line 108:
 ==== Software Setup ==== ==== Software Setup ====
  
-The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called //​**SDK_Workspace**//​ which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA. +<WRAP round info 100%> 
-These are the steps that need to be followed to recreate the software ​project: +Instruction about how to create a software ​application ​can be found [[/resources/fpga/xilinx/software_setup|here]].  
-  * Copy the //​**SDK_Workspace**//​ folder on your PC. Make sure that the path where it is stored does not contain any spaces. +</WRAP>
-  * Copy the no-OS drivers source code to the //​**SDK_Workspace/​sw/​src**//​ folder. +
-{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​src_files.png?​200|no-OS driver Source Files}} +
-  * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder ​can be provided. +
-  * In the SDK select the //**File->​Import**// menu option to import the software projects into the workspace. +
-{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​file_import.png?​200|Import Projects}} +
-  * In the //Import// window select the //​**General->​Existing Projects into Workspace**//​ option. +
-{{:​resources:​eval:​user-guides:​ad-fmcomms1-ebz:​quickstart:​existing_project_import.png?​200|Existing Projects Import}} +
-  * In the //Import Projects// window select the //​**SDK_Workspace**//​ folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //​Projects//​ list. Press //Finish// to finalize the import process+
-{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​projects_import.png?​200|Projects Import}}  +
-  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //​**Project->Build Automatically**//​ menu option. +
-{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​project_explorer.png?​200|Project Explorer}} +
-  * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. +
- +
-The example code is located in the ”//​main.c//​” file and the implementations of the test routines can be found in the "//​cf_ad9467.c//"​ file. +
  
 +The exact location of the no-OS source files can be found in the [[/​resources/​fpga/​xilinx/​fmc/​ad9467#​downloads|Download]] section. ​
   ​   ​
 ===== Downloads ===== ===== Downloads =====
  
-The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\ +The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.
-\\ +
-<WRAP round important 80%> +
-Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[http://​wiki.analog.com/​resources/​eval/​user-guides/​ad-fmcomms1-ebz/​reference_hdl|generating Xilinx netlist/​verilog files from xco files]] for details.\\ +
-\\ +
-The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links below. +
-</​WRAP>​+
  
 **HDL Reference Designs:** **HDL Reference Designs:**
  
-<WRAP round download ​80%+<WRAP round download>​ 
-**Sources for ISE** +**latest release** 
- +  * **ZED HDL Reference Design: ** https://​github.com/​analogdevicesinc/​hdl/​tree/​hdl_2018_r1/​projects/​ad9467_fmc/​zed 
-  * **ML605 HDL Reference Design: ** {{:​resources:​fpga:​xilinx:​fmc:​cf_ad9467_edk_14_4_2013_02_11.tar.gz}} +  * **KC705 HDL Reference Design: ** https://​github.com/​analogdevicesinc/​hdl/​tree/​hdl_2018_r1/​projects/​ad9467_fmc/​kc705
-  * **KC705 HDL Reference Design: ** {{:​resources:​fpga:​xilinx:​fmc:​cf_ad9467_kc705_edk_14_4_2013_02_11.tar.gz}} +
-  * **VC707 HDL Reference Design: ** {{:​resources:​fpga:​xilinx:​fmc:​cf_ad9467_vc707_edk_14_4_2013_02_11.tar.gz}} +
-  * **ZED HDL Reference Design: ​  ** {{:​resources:​fpga:​xilinx:​fmc:​cf_ad9467_zed_edk_14_4_2013_02_11.tar.gz}} +
- +
-**Sources for Vivado** +
-  * **ZED HDL Reference Design: ** https://​github.com/​analogdevicesinc/​hdl/​tree/​master/​projects/​ad9467_fmc/​zed +
-  * **KC705 HDL Reference Design: ** https://​github.com/​analogdevicesinc/​hdl/​tree/​master/​projects/​ad9467_fmc/​kc705+
 </​WRAP>​ </​WRAP>​
  
 **no-OS Software:** **no-OS Software:**
-<WRAP round download ​80%+<WRAP round download>​ 
-  * **AD9467 Driver: ​                  ** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/drivers/AD9467 +**latest release** 
-  * **AD9517 Driver: ​                  ** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/drivers/AD9517 +  * **AD9467 Driver: ​                  ** https://​github.com/​analogdevicesinc/​no-OS/​tree/​2018_R1/drivers/ad9467 
-  * **AD9467-FMC-EBZ Reference Design: ** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/AD9467-FMC-EBZ +  * **AD9517 Driver: ​                  ** https://​github.com/​analogdevicesinc/​no-OS/​tree/​2018_R1/drivers/ad9517 
 +  * **AD9467-FMC-EBZ Reference Design: ** https://​github.com/​analogdevicesinc/​no-OS/​tree/​2018_R1/ad9467-fmc-ebz 
 </​WRAP>​ </​WRAP>​
  
 **Board Files:** **Board Files:**
-<WRAP round download ​80%>+<WRAP round download>​
   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_sch.pdf|Rev C Schematics for the card}}   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_sch.pdf|Rev C Schematics for the card}}
   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_bom.xls|Bill of Materials for Rev C}}   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_bom.xls|Bill of Materials for Rev C}}
-  * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c.zip|AD9467FMC-250EBZ Gerber/​Layout Fabrication Files}}+  * {{ :​resources:​fpga:​xilinx:​fmc:​9467fmc01c.zip|AD9467FMC-250EBZ Gerber/​Layout Fabrication Files}}
 **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM.
 </​WRAP>​ </​WRAP>​
 +===== More information =====
  
-==== Reference Design Contents ==== 
- 
-<WRAP round important 80%> 
-\\ 
-The information below is valid just in case of the XPS projects. The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. ​ 
-</​WRAP>​ 
- 
-^ HDL Reference Design ​  ^^ 
-| license.txt | ADI license & copyright information. | 
-| system.mhs ​ | MHS file. | 
-| system.xmp ​ | XMP file (use this file to build the reference design). | 
-| data/       | UCF file and/or DDR MIG project files. | 
-| docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). | 
-| Chipscope/ ​ | Chipscope project. | 
-| ../​cf_lib/​edk/​pcores/​* | The pcores directory. | 
-^ Software Reference Design ​  ^^ 
-| cf_ad9467.h | Header file containing the registers definitions for the AD9467 HDL core. | 
-| cf_ad9467.c | Implementation of the AD9467 HDL core access functions and ADC test and capture functions. | 
-| spi.h | Header file for the Xilinx AXI SPI driver. | 
-| spi.c | Implementation file for the Xilinx AXI SPI driver. | 
-| main.c | Implementation of the program'​s main function. | 
-^ AD9467 Software Driver ​  ^^ 
-| AD9467.h | AD9467 software driver header file. | 
-| AD9467.c | AD9467 software driver implementation file. | 
-^ AD9517 Software Driver ​  ^^ 
-| AD9517.h | AD9517 software driver header file. | 
-| AD9517_cfg.h | AD9517 software driver configuration file. | 
-| AD9517.c | AD9517 software driver implementation file. | 
-===== More information ===== 
 <WRAP round help 80%> <WRAP round help 80%>
 \\ \\
 [[ez>​community/​fpga|Ask questions about the FPGA reference design]] [[ez>​community/​fpga|Ask questions about the FPGA reference design]]
 </​WRAP>​ </​WRAP>​
resources/fpga/xilinx/fmc/ad9467.1425027600.txt.gz · Last modified: 27 Feb 2015 10:00 by Istvan Csomortani