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+====== AD9467 Native FMC Card / Xilinx Reference Design ======
+===== Introduction =====
+The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the [[adi>AD9517-4]] clock chip and/or setting up the ADL5565 differential amplifier respectively.
+===== Evaluation Board Hardware =====
+To find out more information about the [[http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[http://www.analog.com/media/en/technical-documentation/user-guides/UG-200.pdf|UG200]])
+{{:resources:fpga:xilinx:fmc:ad9467_fmc.jpg?300|}}
+==== Clock Selection ====
+The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467.
+The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.
+The evaluation board can be set up to be clocked from the **crystal oscillator**, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running.
+A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.
+<WRAP round important 100%>
+\\
+Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found at the [[http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467#downloads|Download]] section.
+</WRAP>
+===== Supported Carriers =====
+^ Board     ^ XPS     ^ Vivado     ^
+| [[xilinx>ML605]] |  **DISCONTINUED**  |    |
+| [[xilinx>KC705]] |  **DISCONTINUED**  |  **x**  |
+| [[xilinx>VC707]] |  **DISCONTINUED**  |    |
+| [[http://www.zedboard.org| Zed
+Board]] |  **DISCONTINUED**  |  **x**  |
+==== Other Required Hardware ====
+  * Signal synthesizer (for data and/or clock input).
+==== Required Software ====
+  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/tree/master | git repository ]].
+  * A UART terminal (Tera Term/Hyperterminal), baud rate 115200.
+===== Using the HDL reference design =====
+<WRAP round info 100%>
+Instruction about how to build the HDL design and generate a bit stream, can be found [[http://wiki.analog.com/resources/fpga/docs/hdl#building_hdl|here]].
+</WRAP>
+==== Functional description ====
+The reference design is built on a ARM/Microblaze based system tailored for Linux. A functional block diagram of the design is given below.
+{{:resources:fpga:xilinx:fmc:cf_ad9467_bd.jpg?400|block diagram}}
+Through an SPI interface, the software can access the AD9467/AD9517-4 registers, given the possibility to initialize and configure the ADC and/or clock chip.
+The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
+==== Good To Know ====
+The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted.
+The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the "capture select" bit (register 0x0a, bit 0).
+===== Using the Software Reference Design =====
+The Software Reference Design contains an example on how to:
+  * Initialize the AD9467 evaluation board
+  * Initialize the AD9467 HDL core
+  * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467
+  * Capture data from the AD9467 using DMA transfers
+The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467#downloads|Downloads]] section.
+==== AD9467 Software Driver ====
+Below is presented a short description of all the functions provided in the driver.
+|< 100% 40% 60% >|
+^  Function  ^  Description  ^
+| int32_t **//ad9467_setup//** (int32_t spiBaseAddr, int32_t ssNo) | Configures the test mode and the output mode to a default state. Receives as parameters the SPI peripheral AXI base address and the slave select line on which the slave is connected. Returns negative error code or 0 in case of success.   |
+| int32_t **//ad9467_write//** (uint16_t regAddr, uint8_t regVal) | Writes data into a register. Receives as parameters the address of the register to be written and the value to be written into the register. Returns 0 in case of success or negative error code. |
+| int32_t **//ad9467_read//** (uint16_t regAddr) | Reads data from a register. Receives as parameter the address of the register to be read and returns the read data or negative error code. |
+| int32_t **//ad9467_pwr_mode//** (int32_t mode) | Configures the power mode. Receives as parameter the power mode and returns the negative error code or the set power mode. |
+| int32_t **//ad9467_test_mode//** (int32_t mode) | Sets the ADC's test mode. Receives as parameter the ADC test mode and returns the set test mode or negative error code. |
+| int32_t **//ad9467_reset_PN9//** (int32_t rst) | Sets (1) or clears (0) the reset short PN sequence bit(PN9). Returns the negative error code or the set PN9 status. |
+| int32_t **//ad9467_reset_PN23//** (int32_t rst) | Sets (1) or clears (0) the reset long PN sequence bit(PN23). Returns the negative error code or the set PN23 status. |
+| int32_t **//ad9467_external_ref//** (int32_t en) | Enables (1) or disables (0) the external voltage reference. Returns negative error code or the external reference state. |
+| int32_t **//ad9467_analog_input_disconnect//** (int32_t en) | Disconnects (1) or connects (0) the analog input from or to the ADC channel. Returns the negative error code or the analog disconnect status. |
+| int32_t **//ad9467_offset_adj//** (int32_t adj) | Sets the offset adjustment. Receives as parameter the offset adjust value in LSBs from +127 to -128 and returns the negative error code or the set offset adjustment. |
+| int32_t **//ad9467_output_disable//** (int32_t en) | Disables (1) or enables (0) the data output. Returns the negative error code or the output disable state. |
+| int32_t **//ad9467_output_invert//** (int32_t invert) | Activates the inverted (1) or normal (0) output mode. Returns the negative error code or the set output mode. |
+| int32_t **//ad9467_output_format//** (int32_t format) | Specifies the output format. Receives as parameter the output format and returns the negative error code or the set output format. |
+| int32_t **//ad9467_coarse_LVDS_adj//** (int32_t lvds_adj) | Determines LVDS output properties. Receives as parameter the coarse LVDS adjust and returns the negative error code or LVDS adjust state. |
+| int32_t **//ad9467_output_current_adj//** (int32_t adj) | Sets the output current adjustment. Receives as parameter the output current adjustment and returns the negative error code or the set current adjustment. |
+| int32_t **//ad9467_dco_clock_invert//** (int32_t invert) | Activates the normal (0) or inverted (1) DCO clock. Returns the negative error code or the DCO clock inversion status. |
+| int32_t **//ad9467_dco_output_clock_delay//** (int32_t delay) | Configures the clock delay setting. Receives as parameter the clock delay setting in ps {0, 100, 200, ..., 3100, 3200}. Setting the delay to 0 disables the DCO output clock delay. Returns the negative error code or the set clock delay. |
+| float **//ad9467_full_scale_range//** (float v_fs) | Configures the full-scale input voltage selection. Receives as parameter the full-scale input voltage selection and returns the negative error code or the set input voltage selection. |
+| int32_t **//ad9467_analog_input_coupling//** (int32_t coupling_mode) | Sets the AC coupling(0) or DC coupling(1) mode. Returns the negative error code or the set coupling mode. |
+| int32_t **//ad9467_buffer_current_1//** (int32_t percentage) | Changes the input buffer current(1). Receives as parameter the buffer current and returns negative error code or the set buffer current. |
+| int32_t **//ad9467_buffer_current_2//** (int32_t percentage) | Changes the input buffer current(2). Receives as parameter the buffer current and returns negative error code or the set buffer current. |
+| int32_t **//ad9467_transfer//** (void) | Initiates a transfer and waits for the operation to end. Returns the negative error code or 0 in case of success. |
+==== Software Setup ====
+<WRAP round info 100%>
+Instruction about how to create a software application can be found [[http://wiki.analog.com/resources/fpga/xilinx/software_setup|here]].
+</WRAP>
+The exact location of the no-OS source files can be found in the [[http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467#downloads|Download]] section.
+===== Downloads =====
+The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.
+**HDL Reference Designs:**
+<WRAP round download 80%>
+**Sources for Vivado**
+  * **ZED HDL Reference Design: ** https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9467_fmc/zed
+  * **KC705 HDL Reference Design: ** https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9467_fmc/kc705
+</WRAP>
+**no-OS Software:**
+<WRAP round download 80%>
+  * **AD9467 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/AD9467
+  * **AD9517 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/AD9517
+  * **AD9467-FMC-EBZ Reference Design: ** https://github.com/analogdevicesinc/no-OS/tree/master/AD9467-FMC-EBZ
+</WRAP>
+**Board Files:**
+<WRAP round download 80%>
+  * {{:resources:fpga:xilinx:fmc:9467fmc01c_sch.pdf|Rev C Schematics for the card}}
+  * {{:resources:fpga:xilinx:fmc:9467fmc01c_bom.xls|Bill of Materials for Rev C}}
+  * {{:resources:fpga:xilinx:fmc:9467fmc01c.zip|AD9467FMC-250EBZ Gerber/Layout Fabrication Files}}
+**Note:** C302 and C303 are not installed as indicated in the Schematic and BOM.
+</WRAP>
+===== More information =====
+<WRAP round help 80%>
+\\
+[[ez>community/fpga|Ask questions about the FPGA reference design]]
+</WRAP>

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