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—resources:fpga:xilinx:fmc:ad9467 [27 Feb 2015 10:00] – [Required Hardware] Update for Vivado Istvan Csomortani
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 +====== AD9467 Native FMC Card / Xilinx Reference Design ======
  
 +===== Introduction =====
 +
 +The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the [[adi>AD9517-4]] clock chip and/or setting up the ADL5565 differential amplifier respectively. 
 +
 +===== Supported Devices =====
 +
 +  * [[adi>EVAL-AD9467| AD9467-FMC ]]
 +{{:resources:fpga:xilinx:fmc:ad9467_fmc.jpg?300|}}
 +
 +===== Supported Carriers =====
 +
 +^ Board     ^ XPS     ^ Vivado     ^
 +| [[xilinx>ML605]] |  **DISCONTINUED**  |    |
 +| [[xilinx>KC705]] |  **DISCONTINUED**  |  **x**  |
 +| [[xilinx>VC707]] |  **DISCONTINUED**  |    |
 +| [[http://www.zedboard.org| Zed
 +Board]] |  **DISCONTINUED**  |  **x**  |  
 +
 +<WRAP round important 80%>
 +\\
 +The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. 
 +</WRAP>
 +
 +===== Quick Start Guide =====
 +
 +The reference design has been tested with ML605, KC705, VC707 and Zed. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have.
 +
 +==== Required Hardware ====
 +  * KC705/Zed board
 +  * AD9467-FMC-EBZ board
 +  * Signal generator (for data)
 +  * Signal generator (for clock) (optional)
 +
 +
 +==== Required Software ====
 +
 +  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/tree/master | git repository ]].  
 +  * A UART terminal (Tera Term/Hyperterminal), baud rate 115200.
 +
 +==== Running Demo (SDK) Program ====
 +To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. ** The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). ** However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a clock source to the CLKIN SMA connector and a signal source to the AIN SMA connector of the FMC card. After the hardware setup, turn the power on to the ML605.
 +
 +{{:resources:fpga:xilinx:fmc:cf_ad9467_setup.jpg?200|Hardware setup}}
 +
 +Run the **//download.bat//** script located in the "//SDK/SDK_Workspace/bin//" folder provided within the HDL Reference Design. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR. 
 +
 +**Note:** The //download.bat// script assumes that the //Xilinx ISE Design Suite 14.4// is installed at this path:  //C:/Xilinx/14.4//. If the installation path on your computer is different please modify the script accordingly.
 +
 +If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. 
 +
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_test.png?200|Terminal}}
 +
 +The reference design contains an example on how to:
 +  * Initialize the AD9467 evaluation board
 +  * Initialize the AD9467 HDL core
 +  * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467
 +  * Capture data from the AD9467 using DMA transfers
 +
 +After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "//Chipscope//" folder provided in the HDL Reference Design. These are the steps than need to be followed to view the ADC data in Chipscope:
 +  * open Chipscope and press the **//Open Cable/Search JTAG Chain//** button (the leftmost button located under the File menu)
 +  * open the //Chipscope/AD9467.cpj// project 
 +  * start the data capture
 +This is how the output of the ADC looks like.
 +
 +{{:resources:fpga:xilinx:fmc:cf_ad9467_chipscope.jpg?200|Chipscope Busplot}}
 +===== Using the HDL reference design =====
 +
 +==== Functional description ====
 +
 +The reference design is built on a Microblaze based system parameterized for Linux. A functional block diagram of the design is given below.
 +
 +{{:resources:fpga:xilinx:fmc:cf_ad9467_bd.jpg?400|block diagram}}
 +
 +The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface. 
 +
 +The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
 +
 +
 +==== Registers ====
 +
 +Refer to the **//regmap.txt//** file inside the pcores directory.
 +
 +==== Good To Know ====
 +
 +The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted.
 +
 +The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the "capture select" bit (register 0x0a, bit 0).
 +
 +==== Clock Selection ====
 +
 +The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. 
 +
 +  * External passive clock (default): A SMA connector is provided for an external clock source.
 +  * Optional active clock path or using the AD9517 : You may use either the PECL (OUT3) or the LVDS (OUT5) outputs. The optional oscillator may be used as a clock source for the AD9517 REF or CLK inputs.
 +  * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active (AD9517) path.
 +
 +**Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path.**
 +
 +===== Using the Software Reference Design =====
 +
 +The Software Reference Design contains an example on how to:
 +  * Initialize the AD9467 evaluation board
 +  * Initialize the AD9467 HDL core
 +  * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467
 +  * Capture data from the AD9467 using DMA transfers
 +
 +The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the **Downloads** section.
 +==== AD9467 Software Driver ====
 +
 +Below is presented a short description of all the functions provided in the driver.
 +
 +|< 100% 40% 60% >|
 +^  Function  ^  Description  ^
 +| int32_t **//ad9467_setup//** (int32_t spiBaseAddr, int32_t ssNo) | Configures the test mode and the output mode to a default state. Receives as parameters the SPI peripheral AXI base address and the slave select line on which the slave is connected. Returns negative error code or 0 in case of success.   |
 +| int32_t **//ad9467_write//** (uint16_t regAddr, uint8_t regVal) | Writes data into a register. Receives as parameters the address of the register to be written and the value to be written into the register. Returns 0 in case of success or negative error code. |
 +| int32_t **//ad9467_read//** (uint16_t regAddr) | Reads data from a register. Receives as parameter the address of the register to be read and returns the read data or negative error code. |
 +| int32_t **//ad9467_pwr_mode//** (int32_t mode) | Configures the power mode. Receives as parameter the power mode and returns the negative error code or the set power mode. |
 +| int32_t **//ad9467_test_mode//** (int32_t mode) | Sets the ADC's test mode. Receives as parameter the ADC test mode and returns the set test mode or negative error code. |
 +| int32_t **//ad9467_reset_PN9//** (int32_t rst) | Sets (1) or clears (0) the reset short PN sequence bit(PN9). Returns the negative error code or the set PN9 status. |
 +| int32_t **//ad9467_reset_PN23//** (int32_t rst) | Sets (1) or clears (0) the reset long PN sequence bit(PN23). Returns the negative error code or the set PN23 status. |
 +| int32_t **//ad9467_external_ref//** (int32_t en) | Enables (1) or disables (0) the external voltage reference. Returns negative error code or the external reference state. |
 +| int32_t **//ad9467_analog_input_disconnect//** (int32_t en) | Disconnects (1) or connects (0) the analog input from or to the ADC channel. Returns the negative error code or the analog disconnect status. |
 +| int32_t **//ad9467_offset_adj//** (int32_t adj) | Sets the offset adjustment. Receives as parameter the offset adjust value in LSBs from +127 to -128 and returns the negative error code or the set offset adjustment. |
 +| int32_t **//ad9467_output_disable//** (int32_t en) | Disables (1) or enables (0) the data output. Returns the negative error code or the output disable state. |
 +| int32_t **//ad9467_output_invert//** (int32_t invert) | Activates the inverted (1) or normal (0) output mode. Returns the negative error code or the set output mode. |
 +| int32_t **//ad9467_output_format//** (int32_t format) | Specifies the output format. Receives as parameter the output format and returns the negative error code or the set output format. |
 +| int32_t **//ad9467_coarse_LVDS_adj//** (int32_t lvds_adj) | Determines LVDS output properties. Receives as parameter the coarse LVDS adjust and returns the negative error code or LVDS adjust state. |
 +| int32_t **//ad9467_output_current_adj//** (int32_t adj) | Sets the output current adjustment. Receives as parameter the output current adjustment and returns the negative error code or the set current adjustment. |
 +| int32_t **//ad9467_dco_clock_invert//** (int32_t invert) | Activates the normal (0) or inverted (1) DCO clock. Returns the negative error code or the DCO clock inversion status. |
 +| int32_t **//ad9467_dco_output_clock_delay//** (int32_t delay) | Configures the clock delay setting. Receives as parameter the clock delay setting in ps {0, 100, 200, ..., 3100, 3200}. Setting the delay to 0 disables the DCO output clock delay. Returns the negative error code or the set clock delay. |
 +| float **//ad9467_full_scale_range//** (float v_fs) | Configures the full-scale input voltage selection. Receives as parameter the full-scale input voltage selection and returns the negative error code or the set input voltage selection. |
 +| int32_t **//ad9467_analog_input_coupling//** (int32_t coupling_mode) | Sets the AC coupling(0) or DC coupling(1) mode. Returns the negative error code or the set coupling mode. |
 +| int32_t **//ad9467_buffer_current_1//** (int32_t percentage) | Changes the input buffer current(1). Receives as parameter the buffer current and returns negative error code or the set buffer current. |
 +| int32_t **//ad9467_buffer_current_2//** (int32_t percentage) | Changes the input buffer current(2). Receives as parameter the buffer current and returns negative error code or the set buffer current. |
 +| int32_t **//ad9467_transfer//** (void) | Initiates a transfer and waits for the operation to end. Returns the negative error code or 0 in case of success. |
 +
 +==== Software Setup ====
 +
 +The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called //**SDK_Workspace**// which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA.
 +These are the steps that need to be followed to recreate the software project:
 +  * Copy the //**SDK_Workspace**// folder on your PC. Make sure that the path where it is stored does not contain any spaces.
 +  * Copy the no-OS drivers source code to the //**SDK_Workspace/sw/src**// folder.
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:src_files.png?200|no-OS driver Source Files}}
 +  * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided.
 +  * In the SDK select the //**File->Import**// menu option to import the software projects into the workspace.
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:file_import.png?200|Import Projects}}
 +  * In the //Import// window select the //**General->Existing Projects into Workspace**// option.
 +{{:resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:existing_project_import.png?200|Existing Projects Import}}
 +  * In the //Import Projects// window select the //**SDK_Workspace**// folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //Projects// list. Press //Finish// to finalize the import process.
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:projects_import.png?200|Projects Import}} 
 +  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option.
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:project_explorer.png?200|Project Explorer}}
 +  * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system.
 +
 +The example code is located in the ”//main.c//” file and the implementations of the test routines can be found in the "//cf_ad9467.c//" file. 
 +
 +  
 +===== Downloads =====
 +
 +The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\
 +\\
 +<WRAP round important 80%>
 +Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.\\
 +\\
 +The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links below.
 +</WRAP>
 +
 +**HDL Reference Designs:**
 +
 +<WRAP round download 80%>
 +**Sources for ISE**
 +
 +  * **ML605 HDL Reference Design: ** {{:resources:fpga:xilinx:fmc:cf_ad9467_edk_14_4_2013_02_11.tar.gz}}
 +  * **KC705 HDL Reference Design: ** {{:resources:fpga:xilinx:fmc:cf_ad9467_kc705_edk_14_4_2013_02_11.tar.gz}}
 +  * **VC707 HDL Reference Design: ** {{:resources:fpga:xilinx:fmc:cf_ad9467_vc707_edk_14_4_2013_02_11.tar.gz}}
 +  * **ZED HDL Reference Design:   ** {{:resources:fpga:xilinx:fmc:cf_ad9467_zed_edk_14_4_2013_02_11.tar.gz}}
 +
 +**Sources for Vivado**
 +  * **ZED HDL Reference Design: ** https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9467_fmc/zed
 +  * **KC705 HDL Reference Design: ** https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9467_fmc/kc705
 +</WRAP>
 +
 +**no-OS Software:**
 +<WRAP round download 80%>
 +  * **AD9467 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/AD9467
 +  * **AD9517 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/AD9517
 +  * **AD9467-FMC-EBZ Reference Design: ** https://github.com/analogdevicesinc/no-OS/tree/master/AD9467-FMC-EBZ 
 +</WRAP>
 +
 +**Board Files:**
 +<WRAP round download 80%>
 +  * {{:resources:fpga:xilinx:fmc:9467fmc01c_sch.pdf|Rev C Schematics for the card}}
 +  * {{:resources:fpga:xilinx:fmc:9467fmc01c_bom.xls|Bill of Materials for Rev C}}
 +  * {{:resources:fpga:xilinx:fmc:9467fmc01c.zip|AD9467FMC-250EBZ Gerber/Layout Fabrication Files}}
 +**Note:** C302 and C303 are not installed as indicated in the Schematic and BOM.
 +</WRAP>
 +
 +==== Reference Design Contents ====
 +
 +<WRAP round important 80%>
 +\\
 +The information below is valid just in case of the XPS projects. The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. 
 +</WRAP>
 +
 +^ HDL Reference Design   ^^
 +| license.txt | ADI license & copyright information. |
 +| system.mhs  | MHS file. |
 +| system.xmp  | XMP file (use this file to build the reference design). |
 +| data/       | UCF file and/or DDR MIG project files. |
 +| docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). |
 +| Chipscope/  | Chipscope project. |
 +| ../cf_lib/edk/pcores/* | The pcores directory. |
 +^ Software Reference Design   ^^
 +| cf_ad9467.h | Header file containing the registers definitions for the AD9467 HDL core. |
 +| cf_ad9467.c | Implementation of the AD9467 HDL core access functions and ADC test and capture functions. |
 +| spi.h | Header file for the Xilinx AXI SPI driver. |
 +| spi.c | Implementation file for the Xilinx AXI SPI driver. |
 +| main.c | Implementation of the program's main function. |
 +^ AD9467 Software Driver   ^^
 +| AD9467.h | AD9467 software driver header file. |
 +| AD9467.c | AD9467 software driver implementation file. |
 +^ AD9517 Software Driver   ^^
 +| AD9517.h | AD9517 software driver header file. |
 +| AD9517_cfg.h | AD9517 software driver configuration file. |
 +| AD9517.c | AD9517 software driver implementation file. |
 +===== More information =====
 +<WRAP round help 80%>
 +\\
 +[[ez>community/fpga|Ask questions about the FPGA reference design]]
 +</WRAP>
resources/fpga/xilinx/fmc/ad9467.txt · Last modified: 06 Nov 2023 14:23 by iulia Moldovan

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