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resources:fpga:xilinx:fmc:ad9467 [25 Feb 2023 21:12] – Downloads: Point to "master" branches Dragos Bogdanresources:fpga:xilinx:fmc:ad9467 [25 Apr 2023 16:12] – Add more details to page and restructure it according to the template Iulia Moldovan
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 ===== Introduction ===== ===== Introduction =====
  
-The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the [[adi>AD9517-4]] clock chip and/or setting up the ADL5565 differential amplifier respectively. +The [[adi>AD9467]] chip used on [[adi>eval-ad9467.html | AD9467-FMC-250EBZ]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the [[adi>AD9517-4]] clock chip and/or setting up the ADL5565 differential amplifier respectively. 
  
-===== Evaluation Board Hardware ===== 
  
-To find out more information about the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[adi>media/en/technical-documentation/user-guides/UG-200.pdf|UG200]])+===== Supported devices =====
  
-{{:resources:fpga:xilinx:fmc:ad9467_fmc.jpg?300|}}+  * [[adi>eval-ad9467.html | AD9467-FMC-250EBZ]] also referred to as EVAL-AD9467
  
-==== Clock Selection ==== 
  
-The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. +===== Supported carriers =====
  
-The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.+  * [[xilinx>KC705]] LPC slot 
 +  * [[https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/ | ZedBoard]]
  
-The evaluation board can be set up to be clocked from the **crystal oscillator**, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running. +===== Block design =====
  
-A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi>media/en/technical-documentation/data-sheets/AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.+==== Xilinx block diagram ==== 
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc.svg?500|Xilinx HDL Block Diagram}}
  
-<WRAP round important 100%> +==== AD9467 FMC card block diagram ==== 
-\\ +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc_card.svg?400|Xilinx HDL Block Diagram}}
-Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found at the [[/resources/fpga/xilinx/fmc/ad9467#downloads|Download]] section. +
-</WRAP>+
  
-===== Supported Carriers ===== 
  
-  * [[xilinx>KC705]] LPC Slot +==== Description ====
-  * [[http://www.zedboard.org| ZedBoard]]+
  
-==== Other Required Hardware ====+The reference design is built on a ARM/Microblaze based system tailored for Linux. A functional block diagram of the design is given below.
  
-  * Signal synthesizer (for data and/or clock input).+Through an SPI interface, the software can access the AD9467/AD9517-4 registers, given the possibility to initialize and configure the ADC and/or clock chip.  
  
-==== Required Software ====+The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
  
-  * We're upgrade the Xilinx tools on every release. The supported version number can be found in our HDL [[/resources/fpga/docs/releases | release page]].   
-  * A UART terminal (Tera Term/Hyperterminal), baud rate 115200. 
  
-===== Using the HDL reference design =====+==== Clock selection ====
  
-<WRAP round info 100%> +The board provides three (some modification maybe necessary) possible clock paths for clocking the AD9467, as follows: 
-Instruction about how to build the HDL design and generate a bit stream can be found [[/resources/fpga/docs/build | here]]. + 
 +=== Default clock input === 
 + 
 +The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and AC-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. \\ 
 + 
 +=== Crystal oscillator === 
 + 
 +The evaluation board can be set up to be clocked from the **crystal oscillator**, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000).  
 +  * Install C205 and C206 
 +  * Remove C202 
 +Jumper P200 is used to disable the oscillator from running. \\ 
 + 
 +=== Clock generator AD9517 === 
 + 
 +A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi>media/en/technical-documentation/data-sheets/AD9517-4.pdf|AD9517]]. 
 +  * Populate (C304, C305) for LVPECL clock driver **or** (C306, C307) for LVDS clock driver, with 0.1 µF capacitors 
 +  * Remove C209 and C210 to disconnect the default clock path inputs 
 + 
 +The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.\\ 
 + 
 +<WRAP round important 100%> 
 +Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found {{:resources:fpga:xilinx:fmc:9467fmc01c_sch.pdf?linkonly | here}}.
 </WRAP> </WRAP>
  
-==== Functional description ==== 
  
-The reference design is built on a ARM/Microblaze based system tailored for Linux. A functional block diagram of the design is given below.+==== Hardware description ====
  
-=== Xilinx block diagram === +To find out more information about the [[adi>eval-ad9467.html | AD9467-FMC-250EBZ]] board hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board: [[:resources:eval:ad9467-fmc-250ebz]] and the one of the other board, with an FMC interposer [[adi>media/en/technical-documentation/user-guides/UG-200.pdf|UG200]].
-{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc.svg?500|Xilinx HDL Block Diagram}}+
  
-=== AD9467 FMC Card block diagram === +{{:resources:fpga:xilinx:fmc:ad9467_fmc.jpg?300|}}
-{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc_card.svg?400|Xilinx HDL Block Diagram}}+
  
  
-Through an SPI interface, the software can access the AD9467/AD9517-4 registers, given the possibility to initialize and configure the ADC and/or clock chip.  +===== Quick start guide =====
  
-The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.+==== Required hardware ==== 
 + 
 +  * [[https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/ | ZedBoard]] or [[xilinx>KC705]] board 
 +  * [[adi>eval-ad9467.html | AD9467-FMC-250EBZ]] 
 +  * Signal/clock generator (clock input, 200MHz or 250MHz) 
 +  * Signal generator (analog input, for data capture) 
 +  * Signal synthesizer (for data and/or clock input). 
 + 
 +==== Required software ==== 
 + 
 +  * We're upgrading the Xilinx tools on every release. The supported version number can be found in our HDL [[/resources/fpga/docs/releases | releases page]].   
 +  * A UART terminal (Tera Term/Putty), baud rate 115200. 
 + 
 +===== Using the HDL reference design =====
  
-==== Good To Know ====+Check this wiki page if you're not familiar about [[:resources:fpga:docs:build | how to build an ADI HDL project]].
  
 The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted. The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted.
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 </WRAP> </WRAP>
  
-The exact location of the no-OS source files can be found in the [[/resources/fpga/xilinx/fmc/ad9467#downloads|Download]] section.  +<note important>C302 and C303 are not installed as indicated in the Schematic and BOM.</note>
-   +
-===== Downloads ===== +
- +
-The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github. +
- +
-**HDL Reference Designs:** +
- +
-<WRAP round download> +
-  * **ZED HDL Reference Design: ** [[repo>hdl/tree/master/projects/ad9467_fmc/zed]] +
-  * **KC705 HDL Reference Design: ** [[repo>hdl/tree/master/projects/ad9467_fmc/kc705]] +
-</WRAP> +
- +
-**no-OS Software:** +
-<WRAP round download> +
-  * **AD9467 Driver:                   ** [[repo>no-OS/tree/master/drivers/adc/ad9467]] +
-  * **AD9517 Driver:                   ** [[repo>no-OS/tree/master/drivers/frequency/ad9517]] +
-  * **AD9467-FMC-EBZ Reference Design: ** [[repo>no-OS/tree/master/projects/ad9467]]  +
-</WRAP>+
  
 **Board Files:** **Board Files:**
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   * {{:resources:fpga:xilinx:fmc:9467fmc01c_bom.xls|Bill of Materials for Rev C}}   * {{:resources:fpga:xilinx:fmc:9467fmc01c_bom.xls|Bill of Materials for Rev C}}
   * {{ :resources:fpga:xilinx:fmc:9467fmc01c.zip|AD9467FMC-250EBZ Gerber/Layout Fabrication Files}}   * {{ :resources:fpga:xilinx:fmc:9467fmc01c.zip|AD9467FMC-250EBZ Gerber/Layout Fabrication Files}}
-**Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. 
 </WRAP> </WRAP>
 +
 +
 +===== Resources =====
 +
 +  * [[repo>hdl/tree/master/projects/ad9467_fmc | AD9467_FMC HDL project source code]] with ZedBoard and KC705 carriers
 +  * [[:resources:fpga:docs:axi_ad9467 | AXI_AD9467 IP wiki documentation]]
 +  * [[adi>media/en/technical-documentation/data-sheets/ad9467.pdf | AD9467 chip datasheet]]
 +  * {{:resources:fpga:xilinx:fmc:9467fmc01c_sch.pdf?linkonly | AD9467-FMC-250EBZ schematic}}
 +  * [[repo>no-OS/tree/master/projects/ad9467 | AD9467 no-OS project]]
 +  * [[repo>no-OS/tree/master/drivers/adc/ad9467 | AD9467 no-OS driver]]
 +  * [[repo>no-OS/tree/master/drivers/frequency/ad9517 | AD9517 no-OS driver]]
 +  * [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm/boot/dts/zynq-zed-adv7511-ad9467-fmc-250ebz.dts | AD9467_FMC/Zed Linux devicetree]]
 +  * [[https://github.com/analogdevicesinc/linux/blob/master/arch/microblaze/boot/dts/kc705_ad9467_fmc.dts | AD9467_FMC/KC705 Linux devicetree]]
 +  * [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad9467.c | AD9467 Linux driver]]
 +
 +
 ===== More information ===== ===== More information =====
  
-<WRAP round help 80%> +  * [[:resources:fpga:docs:axi_dmac | High-Speed DMA Controller Peripheral]] wiki documentation 
-\\ +  * [[:resources:fpga:docs:hdl | ADI reference designs HDL user guide]] 
-[[ez>community/fpga|Ask questions about the FPGA reference design]] +  * [[:resources:fpga:docs:arch | ADI HDL architecture]] wiki page 
-</WRAP>+  * [[:resources:fpga:docs:build | How to build an ADI HDL project]] 
 +  * [[:resources:tools-software:linux-software:kuiper-linux | How to prepare an SD card]] with boot files 
 + 
 + 
 +===== Support ===== 
 + 
 +Analog Devices will provide **limited** online support for anyone using the reference design with Analog Devices components via the [[ez>community/fpga | EngineerZone FPGA reference designs]] forum. 
 + 
 +It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers.
resources/fpga/xilinx/fmc/ad9467.txt · Last modified: 06 Nov 2023 14:23 by iulia Moldovan

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