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resources:fpga:xilinx:fmc:ad9467 [15 Nov 2019 10:21]
Stanca-Florina Pop Update block diagram
resources:fpga:xilinx:fmc:ad9467 [03 Jan 2021 22:12]
Robin Getz fix links
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 ===== Evaluation Board Hardware ===== ===== Evaluation Board Hardware =====
  
-To find out more information about the [[http://​www.analog.com/​en/​design-center/​evaluation-hardware-and-software/​evaluation-boards-kits/​EVAL-AD9467.html#​eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[http://​www.analog.com/​media/​en/​technical-documentation/​user-guides/​UG-200.pdf|UG200]])+To find out more information about the [[adi>en/​design-center/​evaluation-hardware-and-software/​evaluation-boards-kits/​EVAL-AD9467.html#​eb-documentation|evaluation board]] hardware, default operation and jumper selection settings please read the Evaluation User Guide of the board. ([[adi>media/​en/​technical-documentation/​user-guides/​UG-200.pdf|UG200]])
  
 {{:​resources:​fpga:​xilinx:​fmc:​ad9467_fmc.jpg?​300|}} {{:​resources:​fpga:​xilinx:​fmc:​ad9467_fmc.jpg?​300|}}
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 The evaluation board can be set up to be clocked from the **crystal oscillator**,​ Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running. ​ The evaluation board can be set up to be clocked from the **crystal oscillator**,​ Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). If this clock source is desired, install C205 and C206 and remove C202. Jumper P200 is used to disable the oscillator from running. ​
  
-A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[http://​www.analog.com/​media/​en/​technical-documentation/​data-sheets/​AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.+A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi>media/​en/​technical-documentation/​data-sheets/​AD9517-4.pdf|AD9517]]. Populate C304, C305, C306, and C307 with 0.1 µF capacitors for one drive option or the other and remove C209 and C210 to disconnect the default clock path inputs. The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.
  
 <WRAP round important 100%> <WRAP round important 100%>
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 === AD9467 FMC Card block diagram === === AD9467 FMC Card block diagram ===
-{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​ad9467_fmc_card.svg?​300|Xilinx HDL Block Diagram}}+{{:​resources:​fpga:​xilinx:​fmc:​ad9467_ebz:​ad9467_fmc_card.svg?​400|Xilinx HDL Block Diagram}}
  
  
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   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_sch.pdf|Rev C Schematics for the card}}   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_sch.pdf|Rev C Schematics for the card}}
   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_bom.xls|Bill of Materials for Rev C}}   * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c_bom.xls|Bill of Materials for Rev C}}
-  * {{:​resources:​fpga:​xilinx:​fmc:​9467fmc01c.zip|AD9467FMC-250EBZ Gerber/​Layout Fabrication Files}}+  * {{ :​resources:​fpga:​xilinx:​fmc:​9467fmc01c.zip|AD9467FMC-250EBZ Gerber/​Layout Fabrication Files}}
 **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM.
 </​WRAP>​ </​WRAP>​
resources/fpga/xilinx/fmc/ad9467.txt · Last modified: 09 Jan 2021 00:39 by Robin Getz