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resources:fpga:xilinx:fmc:ad9434 [27 Oct 2016 11:17] – [Downloads] change ask link Lucian Sinresources:fpga:xilinx:fmc:ad9434 [09 Jan 2021 00:39] – user interwiki links Robin Getz
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-====== AD9434 Native FMC Card & ML605 Xilinx Reference Design ======+ 
 +====== AD9434 Native FMC Card ======
    
 ===== Introduction ===== ===== Introduction =====
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   * [[adi>en/analog-to-digital-converters/ad-converters/ad9434/products/EVAL-AD9434/eb.html| AD9434-FMC-500EBZ]]   * [[adi>en/analog-to-digital-converters/ad-converters/ad9434/products/EVAL-AD9434/eb.html| AD9434-FMC-500EBZ]]
 + 
 +===== Functional Description ======
 +
 +The reference design is built on a Zynq based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
 +By default, the board is configured to use the onboard clock.
 +
  
 ===== Supported Carriers ===== ===== Supported Carriers =====
  
-  * [[xilinx>ZC706]] +  * [[xilinx>ZC706]] LPC Slot 
 +  * [[xilinx>ML605]] Legacy
  
-===== Quick Start Guide =====+===== Downloads ===== 
 + 
 +Board Files: 
 +<WRAP round download 80%> 
 +  * {{:resources:fpga:xilinx:fmc:ad9434_fmc_schematic_wiki.pdf}} 
 +  * {{:resources:fpga:xilinx:fmc:ad9434_fmc_bom_WIKI.xlsx}} 
 +  * {{:resources:fpga:xilinx:fmc:ad9434_fmc_gerbers_wiki.zip}} 
 +</WRAP> 
 + 
 +{{page>resources/fpga/docs/hdl/downloads_insert#ad9434fmc}} 
 + 
 +{{page>resources/fpga/docs/hdl/downloads_insert#help_support}} 
 + 
 +===== ML605 Xilinx Reference Design (Obsolete) ===== 
 + 
 +==== Quick Start Guide ====
  
 The reference design has been tested with ML605. It should be easily portable to other boards such as KC705 and VC707, only the ISERDES primitive, UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). This bit file configuration also captures the test mode outputs of ADC. The reference design has been tested with ML605. It should be easily portable to other boards such as KC705 and VC707, only the ISERDES primitive, UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). This bit file configuration also captures the test mode outputs of ADC.
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 {{:resources:fpga:xilinx:fmc:cf_ad9434_setup.jpg?200|Hardware setup}} {{:resources:fpga:xilinx:fmc:cf_ad9434_setup.jpg?200|Hardware setup}}
  
-Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After reading some default registers in the AD9434 and AD9517, the program enables different test patterns available on the ADC.+Start IMPACT, and initialize the JTAG chain. The program should recognize the Virtex 6 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in the figure below. After reading some default registers in the AD9434 and AD9517, the program enables different test patterns available on the ADC.
  
 {{:resources:fpga:xilinx:fmc:cf_ad9434_uart.jpg?200|Terminal}} {{:resources:fpga:xilinx:fmc:cf_ad9434_uart.jpg?200|Terminal}}
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 {{:resources:fpga:xilinx:fmc:cf_ad9434_busplot.jpg?200|Chipscope Busplot}} {{:resources:fpga:xilinx:fmc:cf_ad9434_busplot.jpg?200|Chipscope Busplot}}
  
-===== Using the reference design =====+==== Using the Reference Design ====
  
-==== Functional description ====+==== Functional Description ====
  
 The reference design is built on a microblaze based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. The reference design is built on a microblaze based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
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 The board provides different (some modification maybe necessary) possible clock path for clocking the AD9434.  The board provides different (some modification maybe necessary) possible clock path for clocking the AD9434. 
  
-===== Downloads ===== +==== Downloads ====
- +
-Board Files: +
-<WRAP round download 80%> +
-  * {{:resources:fpga:xilinx:fmc:ad9434_fmc_schematic_wiki.pdf}} +
-  * {{:resources:fpga:xilinx:fmc:ad9434_fmc_bom_WIKI.xlsx}} +
-  * {{:resources:fpga:xilinx:fmc:ad9434_fmc_gerbers_wiki.zip}} +
-</WRAP> +
 FPGA Referece Designs: FPGA Referece Designs:
 <WRAP round download 80%> <WRAP round download 80%>
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 </WRAP> </WRAP>
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-<WRAP round help 80%> +==== Tar File Contents ====
-  * Questions? [[https://ez.analog.com/community/fpga|Ask Help & Support]]. +
-</WRAP> +
- +
-===== Tar file contents =====+
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 | sw/     | Software (Xilinx SDK) & bit file(s). | | sw/     | Software (Xilinx SDK) & bit file(s). |
 | ../cf_lib/edk/pcores/* | The pcores directory. | | ../cf_lib/edk/pcores/* | The pcores directory. |
- 
-===== More information ===== 
- 
-  * [[ez>community/fpga|Ask questions about the FPGA reference design]] 
- 
- 
  
resources/fpga/xilinx/fmc/ad9434.txt · Last modified: 30 Oct 2023 17:47 by Cristian Mihai Popa

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