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| Both sides previous revisionPrevious revision | Last revisionBoth sides next revision | ||
| resources:fpga:xilinx:fmc:ad9434 [19 Mar 2018 17:29] – Added link to HDL page. Explicitly made the ML605 project obsolete Adrian Costina | resources:fpga:xilinx:fmc:ad9434 [09 Jan 2021 00:39] – user interwiki links Robin Getz | ||
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| - | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http:// | + | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/ |
| ==== Tar File Contents ==== | ==== Tar File Contents ==== | ||
| - | The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/ | + | The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/ |
| | license.txt | ADI license & copyright information. | | | license.txt | ADI license & copyright information. | | ||
resources/fpga/xilinx/fmc/ad9434.txt · Last modified: 30 Oct 2023 17:47 by Cristian Mihai Popa