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—resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:downloads [12 Dec 2012 19:17] – [FMComms1 Downloads] rejeesh kutty
Line 1: Line 1:
 +===== FMComms1 Downloads =====
 +<WRAP round download 80%>
 +  * {{:resources:fpga:xilinx:fmc:fmcomms1-revbschematic.pdf|Schematic}}
 +  * {{:resources:fpga:xilinx:fmc:20_011018b-assy.zip|Assembly Files}}
 +  * {{:resources:fpga:xilinx:fmc:20_011018b.zip|Build Files}}
 +</WRAP>
 +
 +FPGA Reference Designs on GitHub:
 +
 +<WRAP round download 80%>
 +  * https://github.com/analogdevicesinc/fpgahdl_xilinx.git\\
 +  * Latest Tag: **ad_fmcomms1_ebz_edk_14_1_2012_12_12**
 +</WRAP>
 +
 +FPGA Reference Design Tar files:
 +
 +<WRAP round download 80%>
 +  * {{:resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:cf_xcomm_edk_14_1_2012_12_12.tar.gz| ML605}}
 +  * {{:resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:cf_xcomm_kc705_edk_14_1_2012_12_12.tar.gz| KC705}}
 +  * {{:resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:cf_xcomm_vc707_edk_14_1_2012_12_12.tar.gz| VC707}}
 +  * {{:resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:cf_xcomm_zc702_edk_14_1_2012_12_12.tar.gz| ZC702}}
 +  * {{:resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:cf_xcomm_zed_edk_14_1_2012_12_12.tar.gz| Zed}}
 +</WRAP>
 +
 +The GZip file will not contain Xilinx core generator and IP files. You must obtain these files from Xilinx.
 +
 +<WRAP round help 80%>
 +  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].
 +</WRAP>
 + 
 +==== Tar file contents ====
 +
 +The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build 
 +the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
 +
 +In the case of Zynq, the same procedure applies, except that you must create a FSBL or run the PS7 initialization tcl scripts before the SDK program.
 +
 +| license.txt | ADI license & copyright information. |
 +| system.mhs  | MHS file. |
 +| system.xmp  | XMP file (use this file to build the reference design). |
 +| data/       | UCF file and/or DDR MIG project files. |
 +| docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). |
 +| sw/         | Software (Xilinx SDK) & bit file(s). |
 +| cf_lib/edk/pcores | pcores (if used). |
  
resources/fpga/xilinx/fmc/ad-fmcomms1-ebz/downloads.txt · Last modified: 15 Nov 2022 16:16 by Raluca Chis

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