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FPGA Reference Designs on GitHub:
FPGA Reference Design Tar files:
The GZip file will not contain Xilinx core generator and IP files. You must obtain these files from Xilinx.
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
In the case of Zynq, the same procedure applies, except that you must create a FSBL or run the PS7 initialization tcl scripts before the SDK program.
|license.txt||ADI license & copyright information.|
|system.xmp||XMP file (use this file to build the reference design).|
|data/||UCF file and/or DDR MIG project files.|
|docs/||Documentation files (Please note that this wiki page is the documentation for the reference design).|
|sw/||Software (Xilinx SDK) & bit file(s).|
|cf_lib/edk/pcores||pcores (if used).|