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The FMCADC7 reference design is a processor based (ARM, NIOS-II or Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD and ADC cores. The cores are programmable through an AXI-lite interface. The samples are passed to the system memory (DDR).
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.