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| resources:fpga:xilinx:fmc:ad-fmcadc2-ebz [17 Jul 2014 16:09] – Added the No-OS Software Source and the ILA core sections. Dragos Bogdan | resources:fpga:xilinx:fmc:ad-fmcadc2-ebz [20 Dec 2023 11:53] (current) – Add obsolesce notice. Stefan-Robert Raus |
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| ====== ADI AD-FMCADC2-EBZ Boards & Xilinx Reference Design ====== | ====== ADI AD-FMCADC2-EBZ Boards & Xilinx Reference Design ====== |
| | |
| | <note warning>**NOTE:**\\ |
| | Support for the ad-fmcadc2-ebz is discontinued starting with 2022_R2 Kuiper Linux release and it will not be supported in future releases. Last release in which pre-build files can be found is 2021_r2. Check this [[:resources:tools-software:linux-software:adi-kuiper_images:release_notes|link]] to see all Kuiper releases. |
| | </note> |
| | |
| ===== Introduction ===== | ===== Introduction ===== |
| |
| <WRAP important>This design uses the [[http://www.xilinx.com/products/intellectual-property/EF-DI-JESD204.htm|Xilinx JESD204B core]] which requires either a commercial (pay $) or [[http://www.xilinx.com/ipcenter/ipevaluation/jesd204_evaluation.htm|evaluation]] license (eventually pay $) to use. If this is not what you are looking for, you should not use this board.</WRAP> | |
| |
| The [[/resources/eval/user-guides/ad-fmcadc2-ebz|AD-FMCADC2-EBZ]] is a high speed data acquisition (1 ADC channel at 2500 MSPS), in an FMC form factor, which has one high speed JESD204B Analog to Digital converters ([[adi>AD9625]]) on it. The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.5 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures. | The [[/resources/eval/user-guides/ad-fmcadc2-ebz|AD-FMCADC2-EBZ]] is a high speed data acquisition (1 ADC channel at 2500 MSPS), in an FMC form factor, which has one high speed JESD204B Analog to Digital converters ([[adi>AD9625]]) on it. The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.5 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures. |
| ===== Supported Devices ===== | ===== Supported Devices ===== |
| |
| * [[adi>ad9625#product-samples|AD-FMCADC2-EBZ (ADI)]] | * [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC2-EBZ.html#eb-overview|AD-FMCADC2-EBZ]] |
| |
| ===== Supported Carriers ===== | ===== Supported Carriers ===== |
| |
| * [[xilinx> VC707]] HPC Slot | * [[xilinx>VC707]] HPC Slot |
| * [[xilinx> ZC706]] HPC Slot | * [[xilinx>ZC706]] HPC Slot |
| |
| ===== HDL Source ===== | ===== Required Software ===== |
| |
| * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9625_fmc/zc706|ZC706]] | * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/tree/master | git repository ]]. |
| * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9625_fmc/vc707|VC707]] | * A UART terminal (Tera Term/Hyperterminal), baud rate 115200. |
| * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9625x2_fmc/vc707|VC707 Dual AD9625 Board]] | |
| |
| ===== No-OS Software Source ===== | ===== Downloads ===== |
| |
| * {{:resources:fpga:xilinx:fmc:ad9625_fmc_vc707.zip|}} | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github. |
| * {{:resources:fpga:xilinx:fmc:ad9625_fmc_zc706.zip|}} | |
| |
| ===== Quick Start Guide ===== | ===== HDL Source ===== |
| | <WRAP center round download> |
| | * ZC706 HDL Reference design: [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc2/zc706]] |
| | * VC707 HDL Reference design: [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc2/vc707]] |
| | </WRAP> |
| |
| The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming, RF conversion and data capture. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). | |
| |
| ===== ILA core ===== | ===== No-OS Software Source ===== |
| | <WRAP center round download> |
| Many internal signals of the design can be monitored using Vivado Logic Analyzer. | * AD-FMCADC2-EBZ Project - https://github.com/analogdevicesinc/no-OS/tree/master/fmcadc2 |
| | </WRAP> |
| {{:resources:fpga:xilinx:fmc:ad9625_fmc_hw_ila.png?800|}} | |
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