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This version (22 Feb 2017 19:45) was approved by larsc.The Previously approved version (01 Apr 2016 20:59) is available.Diff

AD-FMCADC7-EBZ HDL Reference Design

Functional Overview

The FMCADC7 reference design is a processor based (ARM, NIOS-II or Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-lite interface. The samples are passed to the system memory (DDR).

Control and SPI

The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.

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13 Feb 2015 18:57 · rejeesh
resources/fpga/xilinx/fmc/ad-fmcadc7-ebz.txt · Last modified: 22 Feb 2017 19:44 by larsc