The FMCADC7 reference design is a processor based (ARM, NIOS-II or Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-lite interface. The samples are passed to the system memory (DDR).
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.
Hardware | Project | Carriers | Library Cores |
---|---|---|---|
AD-FMCADC2-EBZ | fmcadc2 | vc707 | axi_ad9625 |
AD-FMCADC3-EBZ | zc706 | axi_adcfifo | |
axi_adxcvr | |||
axi_clkgen | |||
axi_dmac | |||
axi_hdmi_tx | |||
axi_jesd204_common | |||
axi_jesd204_rx | |||
axi_spdif_tx | |||
axi_sysid | |||
jesd204_common | |||
jesd204_rx | |||
sysid_rom | |||
util_adcfifo | |||
util_adxcvr | |||
util_axis_fifo |