This version (22 Feb 2017 19:45) was approved by larsc.The Previously approved version (01 Apr 2016 20:59) is available.
Table of Contents
AD-FMCADC7-EBZ HDL Reference Design
Functional Overview
The FMCADC7 reference design is a processor based (ARM, NIOS-II or Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-lite interface. The samples are passed to the system memory (DDR).
Control and SPI
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.
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FMCADC2/FMCADC3
| Hardware | Project | Carriers | Library Cores |
|---|---|---|---|
| AD-FMCADC2-EBZ | fmcadc2 | vc707 | axi_ad9625 |
| AD-FMCADC3-EBZ | zc706 | axi_adcfifo | |
| axi_adxcvr | |||
| axi_clkgen | |||
| axi_dmac | |||
| axi_hdmi_tx | |||
| axi_jesd204_common | |||
| axi_jesd204_rx | |||
| axi_spdif_tx | |||
| jesd204_common | |||
| jesd204_rx | |||
| util_adcfifo | |||
| util_adxcvr | |||
| util_axis_fifo |
Help & Support
- The carriers (abbrevations can be found here) are commonly available FPGA evaluation boards.
- The HDL user guide contains all the documentation, build instructions and register map tables.
- The following quick links allows you to browse the github repository for a list of current branches, library components, and projects.
resources/fpga/xilinx/fmc/ad-fmcadc7-ebz.txt · Last modified: 22 Feb 2017 19:44 by larsc