ADCs from the Analog Devices Sigma-Delta converter family use a low-level communication protocol that multiplexes the SPI bus MISO signal and the data ready interrupt signal over the same physical wire (DOUT/RDY). The Sigma-Delta SPI Util peripheral can be used to de-multiplex these signals inside a FPGA.
| ||Number of clock cycles after SPI bus activity before data ready is detected.||63|
| ||Chip-select pin used for the Sigma-Delta converter.||0|
| ||Number of total chip-select pins on the SPI bus.||2|
| ||Clock||All other signals are synchronous to this clock.|
| ||Synchronous active low reset||Resets the internal state machine of the core.|
| ||Input||Indicates whether a SPI transaction is active on the SPI bus. (Active high).|
| ||Output||Indicates when a data ready condition is detected. (Active high).|
| ||SPI bus interface slave||SPI bus interface connected to the upstream SPI controller.|
| ||SPI bus interface master||SPI bus interface connected to the downstream SPI bus.|
The Sigma-Delta Util Peripheral monitors the SPI bus that is connected to the
s_spi interface for the converters data ready condition. The
m_spi interface is directly connected to the
s_spi interface. In a typical configuration the
s_spi interface is connected to a SPI controller and the
m_spi interface is connected to external SPI bus pins.
data_ready signal is level active high and will be asserted as long as the data ready condition is detected. It can for example be connected to a interrupt controller to start a interrupt service routine that will read the converted data sample from the ADC or it can be connected to a HDL block like the SPI Engine Offload block that will generate a SPI transaction to read the converted signal.
The data ready condition is only detected if the chip-select signal which is connected to the converter is asserted and the
spi_active signal is de-asserted and both signals have been in that state for at least
IDLE_TIMEOUT clock cycles. The timeout is used to avoid spurious signal detection and the
IDLE_TIMEOUT parameter should be configured so that the period it takes to complete
IDLE_TIMEOUT clock cycles with the
clk clock is larger than the “CS falling edge to DOUT/RDY active time” and “SCLK inactive edge to DOUT/RDY high/low” as specified in the datasheet for the converter.