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resources:fpga:peripherals:spi_engine [11 Oct 2021 15:26] – Edit path in footer Iulia Moldovanresources:fpga:peripherals:spi_engine [13 Oct 2021 08:45] – Edit footer Iulia Moldovan
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 The core component of the SPI Engine framework is a lean but powerful fully programmable execution module, which implements the SPI bus control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example a software controlled memory mapped command stream offers high flexibility, while a offload core which executes a pre-programmed command stream when triggered by an external event allows for very low latency response times. By using a SPI Engine interconnect it is possible to connect multiple command stream master modules to a SPI Engine execution module. The core component of the SPI Engine framework is a lean but powerful fully programmable execution module, which implements the SPI bus control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example a software controlled memory mapped command stream offers high flexibility, while a offload core which executes a pre-programmed command stream when triggered by an external event allows for very low latency response times. By using a SPI Engine interconnect it is possible to connect multiple command stream master modules to a SPI Engine execution module.
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 ===== Sub-modules ===== ===== Sub-modules =====
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   * [[.:spi_engine:offload|Offload Module]]: Stores a SPI Engine command stream, execution is triggered by an external event   * [[.:spi_engine:offload|Offload Module]]: Stores a SPI Engine command stream, execution is triggered by an external event
   * [[.:spi_engine:interconnect|Interconnect Module]]: Connects multiple SPI Engine command streams to a SPI Engine execution module   * [[.:spi_engine:interconnect|Interconnect Module]]: Connects multiple SPI Engine command streams to a SPI Engine execution module
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 ===== Interfaces ===== ===== Interfaces =====
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   * [[.:spi_engine:spi_engine_offload_control_interface|SPI Engine Offload Control Interface]]: Program the command stream stored in a offload module   * [[.:spi_engine:spi_engine_offload_control_interface|SPI Engine Offload Control Interface]]: Program the command stream stored in a offload module
   * [[.:spi_engine:spi_bus_interface|SPI Bus Interface]]: Low-level SPI bus interface   * [[.:spi_engine:spi_bus_interface|SPI Bus Interface]]: Low-level SPI bus interface
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 ===== Software ===== ===== Software =====
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   * [[util_sigma_delta_spi|Sigma-Delta SPI Util]]: Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family   * [[util_sigma_delta_spi|Sigma-Delta SPI Util]]: Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family
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 ===== Examples ===== ===== Examples =====
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   * [[resources:eval:user-guides:ad7768-1]] - The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC).   * [[resources:eval:user-guides:ad7768-1]] - The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC).
   * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad40xx_fmc|AD40xx-FMC]] - Evaluation Board for the AD4000 Series 16-/18-/20-Bit Precision SAR ADCs   * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad40xx_fmc|AD40xx-FMC]] - Evaluation Board for the AD4000 Series 16-/18-/20-Bit Precision SAR ADCs
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 ===== Additional Documents ===== ===== Additional Documents =====
  
   * {{:resources:fpga:peripherals:spi-engine3.pdf|Presentation: SPI Engine Design Philosophy}}   * {{:resources:fpga:peripherals:spi-engine3.pdf|Presentation: SPI Engine Design Philosophy}}
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-{{navigation HDL User Guide#../docs/axi_ip|AXI IP cores#../docs/hdl|Main page#../docs/tips|Using and modifying the HDL design}}+ 
 +{{navigation HDL User Guide#../docs/ip_cores|IP cores#../docs/hdl|Main page#../docs/tips|Using and modifying the HDL design}}
resources/fpga/peripherals/spi_engine.txt · Last modified: 22 Dec 2022 13:07 by sergiu arpadi

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