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resources:fpga:peripherals:spi_engine:spi_bus_interface [06 Oct 2016 17:27] – [Example Verilog IO configuration] Lars-Peter Clausenresources:fpga:peripherals:spi_engine:spi_bus_interface [11 May 2018 17:42] (current) – [Files] Switch to master branch Istvan Csomortani
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 ^ Name ^ Description ^ ^ Name ^ Description ^
-| [[github>hdl?dev/library/spi_engine/interfaces/spi_master_rtl.xml|spi_master_rtl.xml]] | Interface definition file |+| [[github>hdl?master/library/spi_engine/interfaces/spi_master_rtl.xml|spi_master_rtl.xml]] | Interface definition file |
 ===== Signal Pins ===== ===== Signal Pins =====
  
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 | ''sdo'' | Output | SPI SDO (MOSI) signal. | | ''sdo'' | Output | SPI SDO (MOSI) signal. |
 | ''sdo_t'' | Output | ''sdo'' tri-state enable. If 1 the MOSI signal should be tristated and not be connected to ''sdo''  | | ''sdo_t'' | Output | ''sdo'' tri-state enable. If 1 the MOSI signal should be tristated and not be connected to ''sdo''  |
-| ''sdi'' | Input | SPI SDI (MISO) signal. |+| ''sdi'' | Input | SPI SDI (MISO) signal. Execution module supports max 8 individual ''sdi'' lines. |
 | ''cs'' | Output | SPI chip-select signal. | | ''cs'' | Output | SPI chip-select signal. |
 | ''three_wire'' | Output | If set to 1 the bus should operate in three-wire mode. In three-wire mode ''sdi'' is connected to MOSI instead of MISO. | | ''three_wire'' | Output | If set to 1 the bus should operate in three-wire mode. In three-wire mode ''sdi'' is connected to MOSI instead of MISO. |
resources/fpga/peripherals/spi_engine/spi_bus_interface.txt · Last modified: 11 May 2018 17:42 by Istvan Csomortani