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resources:fpga:peripherals:spi_engine:offload [27 Mar 2015 10:41] Lars-Peter Clausenresources:fpga:peripherals:spi_engine:offload [19 Apr 2023 21:47] (current) – [Signal and Interface Pins] Jorge Marques
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 ^ Name ^ Description ^ ^ Name ^ Description ^
-| .v | Verilog source for the peripheral. | +[[github>hdl?master/library/spi_engine/spi_engine_offload/spi_engine_offload.v|spi_engine_offload.v]] | Verilog source for the peripheral. | 
-| .tcl | TCL script to generate the Vivado IP-integrator project for the peripheral. |+[[github>hdl?master/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl|spi_engine_offload_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |
  
 ===== Configuration Parameters ===== ===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default ^ ^ Name ^ Description ^ Default ^
 +| ''SPI_CLK_ASYNC'' | If set to 1 the ''ctrl_clk'' and ''spi_clk'' are assumed to be asynchronous | 0 |
 | ''CMD_MEM_ADDR_WIDTH'' | Configures the size of the command stream storage. The size is ''2<nowiki>**</nowiki>CMD_MEM_ADDR_WIDTH'' entries. |  4 | | ''CMD_MEM_ADDR_WIDTH'' | Configures the size of the command stream storage. The size is ''2<nowiki>**</nowiki>CMD_MEM_ADDR_WIDTH'' entries. |  4 |
 | ''SDO_MEM_ADDR_WIDTH'' | Configures the size of the SDO data stream storage. The size is ''2<nowiki>**</nowiki>SDO_MEM_ADDR_WIDTH'' entries. |  4 | | ''SDO_MEM_ADDR_WIDTH'' | Configures the size of the SDO data stream storage. The size is ''2<nowiki>**</nowiki>SDO_MEM_ADDR_WIDTH'' entries. |  4 |
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 ^ Name ^ Type ^ Description ^ ^ Name ^ Type ^ Description ^
 | ''ctrl_clk'' | Clock | The ''spi_engine_offload_ctrl'' signals are synchronous to this clock. | | ''ctrl_clk'' | Clock | The ''spi_engine_offload_ctrl'' signals are synchronous to this clock. |
-| ''spi_clk'' | Clock | The ''spi_engine_ctrl'' siganls, ''offload_sdi'' signals and trigger are synchronous to this clock. |+| ''spi_clk'' | Clock | The ''spi_engine_ctrl'' signals, ''offload_sdi'' signals and trigger are synchronous to this clock. |
 | ''spi_resetn'' | Synchronous active low reset | Resets the internal state machine of the core. | | ''spi_resetn'' | Synchronous active low reset | Resets the internal state machine of the core. |
 | ''trigger'' | Input | When asserted the stored command and data stream is send out on the ''spi_engine_ctrl'' interface. | | ''trigger'' | Input | When asserted the stored command and data stream is send out on the ''spi_engine_ctrl'' interface. |
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 | ''spi_engine_ctrl'' | [[SPI Engine Control Interface]] master | SPI Engine Control stream that contains commands and data. | | ''spi_engine_ctrl'' | [[SPI Engine Control Interface]] master | SPI Engine Control stream that contains commands and data. |
 | ''offload_sdi'' | Streaming AXI master | Output stream of the received SPI data | | ''offload_sdi'' | Streaming AXI master | Output stream of the received SPI data |
 +
 ===== Theory of Operation ===== ===== Theory of Operation =====
 +
 +===== More Information =====
 +  * [[.|SPI Engine Framework]]
resources/fpga/peripherals/spi_engine/offload.1427449273.txt.gz · Last modified: 27 Mar 2015 10:41 by Lars-Peter Clausen