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resources:fpga:peripherals:spi_engine:offload [27 May 2015 14:19] – [Configuration Parameters] Lars-Peter Clausenresources:fpga:peripherals:spi_engine:offload [19 Apr 2023 21:47] (current) – [Signal and Interface Pins] Jorge Marques
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 ^ Name ^ Description ^ ^ Name ^ Description ^
-| [[github>hdl?dev/library/spi_engine/spi_engine_offload/spi_engine_offload.v|spi_engine_offload.v]] | Verilog source for the peripheral. | +| [[github>hdl?master/library/spi_engine/spi_engine_offload/spi_engine_offload.v|spi_engine_offload.v]] | Verilog source for the peripheral. | 
-| [[github>hdl?dev/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl|spi_engine_offload_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |+| [[github>hdl?master/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl|spi_engine_offload_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |
  
 ===== Configuration Parameters ===== ===== Configuration Parameters =====
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 ^ Name ^ Type ^ Description ^ ^ Name ^ Type ^ Description ^
 | ''ctrl_clk'' | Clock | The ''spi_engine_offload_ctrl'' signals are synchronous to this clock. | | ''ctrl_clk'' | Clock | The ''spi_engine_offload_ctrl'' signals are synchronous to this clock. |
-| ''spi_clk'' | Clock | The ''spi_engine_ctrl'' siganls, ''offload_sdi'' signals and trigger are synchronous to this clock. |+| ''spi_clk'' | Clock | The ''spi_engine_ctrl'' signals, ''offload_sdi'' signals and trigger are synchronous to this clock. |
 | ''spi_resetn'' | Synchronous active low reset | Resets the internal state machine of the core. | | ''spi_resetn'' | Synchronous active low reset | Resets the internal state machine of the core. |
 | ''trigger'' | Input | When asserted the stored command and data stream is send out on the ''spi_engine_ctrl'' interface. | | ''trigger'' | Input | When asserted the stored command and data stream is send out on the ''spi_engine_ctrl'' interface. |
resources/fpga/peripherals/spi_engine/offload.txt · Last modified: 19 Apr 2023 21:47 by Jorge Marques