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resources:fpga:peripherals:spi_engine:interconnect [26 May 2015 18:57] – [Files] Lars-Peter Clausenresources:fpga:peripherals:spi_engine:interconnect [04 Sep 2019 12:47] (current) – Add configuration parameters, fix some grammar mistakes Istvan Csomortani
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 {{ :resources:fpga:peripherals:spi_engine:spi_engine_interconnect.png|}} {{ :resources:fpga:peripherals:spi_engine:spi_engine_interconnect.png|}}
  
-The SPI Engine Interconnect module allows to connect multiple [[SPI Engine Control Interface]] masters to a single [[SPI Engine Control Interface]] slave. This enables multiple command stream generators to connect to a single [[engine|SPI Engine Execution module]] and consequential give them access to the same SPI bus. The interconnect modules takes care of properly arbitrating between the different command streams.+The SPI Engine Interconnect module allows connecting multiple [[SPI Engine Control Interface]] masters to a single [[SPI Engine Control Interface]] slave. This enables multiple command stream generators to connect to a single [[engine|SPI Engine Execution module]] and consequential give them access to the same SPI bus. The interconnect modules take care of properly arbitrating between the different command streams.
  
-Combining multiple command stream generators in a design and connecting them to a single execution modules allows for the creation of flexible and efficient designs using standard components.+Combining multiple command stream generators in a design and connecting them to a single execution module allows for the creation of flexible and efficient designs using standard components.
  
 ===== Files ===== ===== Files =====
  
 ^ Name ^ Description ^ ^ Name ^ Description ^
-| [[github>hdl?dev/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v|spi_engine_interconnect.v]] | Verilog source for the peripheral. | +| [[github>hdl?master/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v|spi_engine_interconnect.v]] | Verilog source for the peripheral. | 
-| [[github>hdl?dev/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl|spi_engine_interconnect_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |+| [[github>hdl?master/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl|spi_engine_interconnect_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |
  
 ===== Configuration Parameters ===== ===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default ^ ^ Name ^ Description ^ Default ^
 +| ''DATA_WIDTH'' | Data width of the parallel SDI/SDO data interfaces. | 8 |
 +| ''NUM_OF_SDI'' | Number of SDI lines on the physical SPI interface. | 1 |
  
 ===== Signal and Interface Pins ===== ===== Signal and Interface Pins =====
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 ^ Name ^ Type ^ Description ^ ^ Name ^ Type ^ Description ^
 | clk | Clock | A signals of the module are synchronous to this clock. | | clk | Clock | A signals of the module are synchronous to this clock. |
-| resetn | Synchronous active low reset | Resets the internal state of the module. |+| resetn | Synchronous active-low reset | Resets the internal state of the module. |
 | s0_ctrl | [[SPI Engine Control Interface]] slave | Connects to the first control interface master | | s0_ctrl | [[SPI Engine Control Interface]] slave | Connects to the first control interface master |
 | s1_ctrl | [[SPI Engine Control Interface]] slave | Connects to the second control interface master | | s1_ctrl | [[SPI Engine Control Interface]] slave | Connects to the second control interface master |
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 ===== Theory of Operation ===== ===== Theory of Operation =====
  
-The SPI Engine Interconnect module has multiple [[SPI Engine Control Interface]] slave ports and a single [[SPI Engine Control Interface]] master port. It can be used to connect multiple command stream generators to a single command execution engine. Arbitration between the streams is done on a priority basis, streams with a lower index have higher priority. This means if commands are present on two streams arbitration will be granted to the one with the lower index. Once arbitration has been granted the port it was granted to stays in control until it sends a SYNC command. When the interconnect module sees a SYNC command arbitration will re-evaluated after the SYNC command has been completed. This makes sure that once a SPI transaction consisting of multiple commands has been started it is able to complete without being interrupted by a higher priority stream.+The SPI Engine Interconnect module has multiple [[SPI Engine Control Interface]] slave ports and a single [[SPI Engine Control Interface]] master port. It can be used to connect multiple command stream generators to a single command execution engine. Arbitration between the streams is done on a priority basis, streams with a lower index have higher priority. This means if commands are present on two streams arbitration will be granted to the one with the lower index. Once arbitration has been granted the port it was granted to stays in control until it sends a SYNC command. When the interconnect module sees a SYNC command arbitration will be re-evaluated after the SYNC command has been completed. This makes sure that once a SPI transaction consisting of multiple commands has been started it is able to complete without being interrupted by a higher priority stream.
  
 ===== More Information ===== ===== More Information =====
   * [[.|SPI Engine Framework]]   * [[.|SPI Engine Framework]]
resources/fpga/peripherals/spi_engine/interconnect.1432659439.txt.gz · Last modified: 26 May 2015 18:57 by Lars-Peter Clausen

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