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resources:fpga:peripherals:spi_engine:interconnect [11 May 2018 17:47]
Istvan Csomortani [Files] Switch to master
resources:fpga:peripherals:spi_engine:interconnect [04 Sep 2019 12:47]
Istvan Csomortani Add configuration parameters, fix some grammar mistakes
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 {{ :​resources:​fpga:​peripherals:​spi_engine:​spi_engine_interconnect.png|}} {{ :​resources:​fpga:​peripherals:​spi_engine:​spi_engine_interconnect.png|}}
  
-The SPI Engine Interconnect module allows ​to connect ​multiple [[SPI Engine Control Interface]] masters to a single [[SPI Engine Control Interface]] slave. This enables multiple command stream generators to connect to a single [[engine|SPI Engine Execution module]] and consequential give them access to the same SPI bus. The interconnect modules ​takes care of properly arbitrating between the different command streams.+The SPI Engine Interconnect module allows ​connecting ​multiple [[SPI Engine Control Interface]] masters to a single [[SPI Engine Control Interface]] slave. This enables multiple command stream generators to connect to a single [[engine|SPI Engine Execution module]] and consequential give them access to the same SPI bus. The interconnect modules ​take care of properly arbitrating between the different command streams.
  
-Combining multiple command stream generators in a design and connecting them to a single execution ​modules ​allows for the creation of flexible and efficient designs using standard components.+Combining multiple command stream generators in a design and connecting them to a single execution ​module ​allows for the creation of flexible and efficient designs using standard components.
  
 ===== Files ===== ===== Files =====
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 ^ Name ^ Description ^ Default ^ ^ Name ^ Description ^ Default ^
 +| ''​DATA_WIDTH''​ | Data width of the parallel SDI/SDO data interfaces. | 8 |
 +| ''​NUM_OF_SDI''​ | Number of SDI lines on the physical SPI interface. | 1 |
  
 ===== Signal and Interface Pins ===== ===== Signal and Interface Pins =====
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 ^ Name ^ Type ^ Description ^ ^ Name ^ Type ^ Description ^
 | clk | Clock | A signals of the module are synchronous to this clock. | | clk | Clock | A signals of the module are synchronous to this clock. |
-| resetn | Synchronous active low reset | Resets the internal state of the module. |+| resetn | Synchronous active-low reset | Resets the internal state of the module. |
 | s0_ctrl | [[SPI Engine Control Interface]] slave | Connects to the first control interface master | | s0_ctrl | [[SPI Engine Control Interface]] slave | Connects to the first control interface master |
 | s1_ctrl | [[SPI Engine Control Interface]] slave | Connects to the second control interface master | | s1_ctrl | [[SPI Engine Control Interface]] slave | Connects to the second control interface master |
resources/fpga/peripherals/spi_engine/interconnect.txt · Last modified: 04 Sep 2019 12:47 by Istvan Csomortani