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SPI Engine Execution FPGA Peripheral

The SPI Engine Execution peripheral forms the heart of the SPI Engine framework. It is responsible for handling a SPI Engine control stream and translate it into low-level SPI bus transactions.


Name Description
spi_engine_execution.v Verilog source for the peripheral.
spi_engine_execution_ip.tcl TCL script to generate the Vivado IP-integrator project for the peripheral.

Configuration Parameters

Name Description Default
NUM_CS Number of chip-select signals for the SPI bus (min: 1, max: 8) 1
DEFAULT_SPI_CFG Reset configuration value for the SPI configuration register 0
DEFAULT_CLK_DIV Reset configuration value for the prescaler clock divider register 0
DATA_WIDTH Data width of the parallel data stream. Will define the transaction's granularity. Supported values: 8/16/24/32 8
NUM_OF_SDI Number of multiple SDI lines, (min: 1, max: 8) 1

Signal and Interface Pins

Name Type Description
clk Clock All other signals are synchronous to this clock.
resetn Synchronous active low reset Resets the internal state machine of the core.
active Output Indicates whether the peripheral is currently active and processing commands.
ctrl SPI Engine Control Interface slave SPI Engine Control stream that contains commands and data for the execution module.
spi SPI bus interface master Low-level SPI bus interface that is controlled by peripheral.

Theory of Operation

The SPI Engine Execution module implements the physical access to the SPI bus. It implements a small but powerful programmable state machine that translates a SPI Engine command stream into low-level SPI bus access.

Communication with a command stream generator happens via the ctrl interface and the low-level SPI access is handled on the spi interface. The active signal is asserted as long as the peripheral is busy executing incoming commands.

Internally the SPI Engine execution module consist of a instruction encoder that translates the incoming commands into internal control signal, a multi-function counter and compare unit that is responsible for handling the timing and a shift register which holds the received and transmitted SPI data.

The module has an optional programmable pre-scaler register that can be used to divide the external clock to the counter and compare unit.

More Information

resources/fpga/peripherals/spi_engine/engine.1526053024.txt.gz · Last modified: 11 May 2018 17:37 by Istvan Csomortani