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resources:fpga:peripherals:jesd204 [15 Apr 2020 13:06] – [JESD204C Mixed-Signal Front Ends] Laszlo Nagyresources:fpga:peripherals:jesd204 [22 Apr 2020 13:28] – [Link Layer] Laszlo Nagy
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 ====== JESD204 Interface Framework ====== ====== JESD204 Interface Framework ======
  
-The JESD204, JESD204A and the JESD204B data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.+The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.
  
-Analog Devices supplies a full-stack supporting JESD204B which provides a fully integrated system level experience. This solution includes +Analog Devices supplies a full-stack supporting JESD204B/C which provides a fully integrated system level experience. This solution includes 
 <WRAP round download 65%> <WRAP round download 65%>
   * [[#jesd204b_rapid_prototyping_platforms|Reference hardware platforms]] for rapid-prototyping   * [[#jesd204b_rapid_prototyping_platforms|Reference hardware platforms]] for rapid-prototyping
-  * [[#fpga_hdl_support|FPGA HDL]] for interfacing JESD204B ADCs, DACs, and RF Transceivers +  * [[#fpga_hdl_support|FPGA HDL]] for interfacing JESD204B/C ADCs, DACs, and RF Transceivers 
   * [[#software_support|Software]] to configure the converter devices and FPGA HDL peripherals    * [[#software_support|Software]] to configure the converter devices and FPGA HDL peripherals 
 </WRAP> </WRAP>
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 {{ :resources:fpga:peripherals:jesd204_layers2.png?100|}} {{ :resources:fpga:peripherals:jesd204_layers2.png?100|}}
  
-The JESD204B standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B protocol processing chain.+The JESD204B/C standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B/C HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B/C protocol processing chain.
  
 Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used. Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used.
  
-The link layer component is selected based on the direction of the JESD204B link.+The link layer component is selected based on the direction of the JESD204B/C link.
  
 The application layer is user defined and can be used to implement application specific signal processing. The application layer is user defined and can be used to implement application specific signal processing.
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 ==== Link Layer ==== ==== Link Layer ====
  
-Link layer peripherals are responsible for JESD204B protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring.+Link layer peripherals are responsible for JESD204B/C protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring.
  
-  * [[.:jesd204:axi_jesd204_tx|JESD204B Transmit Peripheral]]: JESD204B Link Layer Transmit Peripheral +  * [[.:jesd204:axi_jesd204_tx|JESD204B/C Transmit Peripheral]]: JESD204B/C Link Layer Transmit Peripheral 
-  * [[.:jesd204:axi_jesd204_rx|JESD204B Receive Peripheral]]: JESD204B Link Layer Receive Peripheral+  * [[.:jesd204:axi_jesd204_rx|JESD204B/C Receive Peripheral]]: JESD204B/C Link Layer Receive Peripheral
  
 ==== Transport Layer ==== ==== Transport Layer ====
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 Transport layer peripherals are responsible for converter specific data framing and de-framing. Transport layer peripherals are responsible for converter specific data framing and de-framing.
  
-  * [[resources:fpga:peripherals:jesd204:jesd204_tpl_adc|ADC JESD204B Transport Peripheral]] : JESD204B Transport Layer Receive Peripheral  +  * [[resources:fpga:peripherals:jesd204:jesd204_tpl_adc|ADC JESD204B/C Transport Peripheral]] : JESD204B/C Transport Layer Receive Peripheral  
-  * [[resources:fpga:peripherals:jesd204:jesd204_tpl_dac|DAC JESD204B Transport Peripheral]] : JESD204B Transport Layer Transmit Peripheral +  * [[resources:fpga:peripherals:jesd204:jesd204_tpl_dac|DAC JESD204B/C Transport Peripheral]] : JESD204B/C Transport Layer Transmit Peripheral 
  
 ==== Interfaces ==== ==== Interfaces ====
  
-Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B processing stack.+Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B/C processing stack.
 ===== Software Support ===== ===== Software Support =====
  
resources/fpga/peripherals/jesd204.txt · Last modified: 25 Mar 2024 08:30 by Paul Pop

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