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resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [12 Jun 2018 19:57] – [References] Use wiki links for internal links Lars-Peter Clausenresources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [14 Jan 2021 05:38] (current) – use wiki interwiki links Robin Getz
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 ====== DAQ2 HDL Project for Xilinx ====== ====== DAQ2 HDL Project for Xilinx ======
  
-===== Xilinx Block Diagram ===== +The reference design is a processor based embedded system. The sources are split into three different folders:
- +
-{{:resources:eval:user-guides:ad-fmcdaq2-ebz:daq2_bd_v3.jpg?800|Xilinx HDL Block Diagram}} +
- +
- The reference design is a processor based embedded system. The sources are split into three different folders:+
   * base design for the carrier board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/common | /projects/common]] where all generic peripherals are instantiated. Here we do most of the PS8 configuration, add SPI, I2C and GPIOs. In some cases, we have scripts to instantiate also the PL DDR as ADC offload memory or DAC offload memory   * base design for the carrier board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/common | /projects/common]] where all generic peripherals are instantiated. Here we do most of the PS8 configuration, add SPI, I2C and GPIOs. In some cases, we have scripts to instantiate also the PL DDR as ADC offload memory or DAC offload memory
   * base design for the evaluation board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/common | /projects/daq2/common]], where all the IPs to control the DAQ2 evaluation board are instantiated, in a way in which it can be integrated with most of the carriers that we support   * base design for the evaluation board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/common | /projects/daq2/common]], where all the IPs to control the DAQ2 evaluation board are instantiated, in a way in which it can be integrated with most of the carriers that we support
   * specific design for the project, in our case the ZCU102 [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/zcu102 | /projects/daq2/zcu102]]. Here, we source the carrier board configuration, then the evaluation board configuration and then we do some specific parameter modification, if required. In this folder, the constraints and ''system_top.v'' are also defined.   * specific design for the project, in our case the ZCU102 [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/zcu102 | /projects/daq2/zcu102]]. Here, we source the carrier board configuration, then the evaluation board configuration and then we do some specific parameter modification, if required. In this folder, the constraints and ''system_top.v'' are also defined.
  
-The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface.+ 
 +==== AD-FMCDAQ2-EBZ block diagram ==== 
 +{{resources:eval:user-guides:ad-fmcdaq2-ebz:AD-FMCDAQ2-EBZ_1.svg?600|Xilinx HDL Block Diagram}} 
 + 
 +==== Xilinx block diagram ==== 
 +{{resources:eval:user-guides:ad-fmcdaq2-ebz:daq2_xilinx_2.svg?800|Xilinx HDL Block Diagram}} 
 + 
 + The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface.
  
 The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps, by default. The transceivers interface the ADC/DAC cores at 128bits@250MHz. The data is sent or received based on the configuration of separate transmit and receive chains. The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps, by default. The transceivers interface the ADC/DAC cores at 128bits@250MHz. The data is sent or received based on the configuration of separate transmit and receive chains.
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 ===== Building the HDL Project ===== ===== Building the HDL Project =====
  
-When building the project, you should always use the recommended version of the tools for the specific [[https://wiki.analog.com/resources/fpga/docs/releases | release]]. In this example, we'll use release 2018_r1, which has Vivado 2017.4.1 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.+When building the project, you should always use the recommended version of the tools for the specific [[/resources/fpga/docs/releases | release]]. In this example, we'll use release 2018_r1, which has Vivado 2017.4.1 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.
  
 <code> <code>
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 ===== References ===== ===== References =====
  
-[[resources/fpga/docs/build|HDL Build Instruction]] \\+[[resources/fpga/docs/build|HDL Build Instructions]] \\
 [[resources/tools-software/linux-software/build-the-zynqmp-boot-image|How to build the ZynqMP boot image BOOT.BIN]] \\ [[resources/tools-software/linux-software/build-the-zynqmp-boot-image|How to build the ZynqMP boot image BOOT.BIN]] \\
 [[resources/tools-software/linux-software/build-the-zynq-boot-image|How to build the Zynq boot image BOOT.BIN]] \\ [[resources/tools-software/linux-software/build-the-zynq-boot-image|How to build the Zynq boot image BOOT.BIN]] \\
  
resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx.1528826220.txt.gz · Last modified: 12 Jun 2018 19:57 by Lars-Peter Clausen

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