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resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [15 May 2018 14:22] – created Adrian Costinaresources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [14 Jan 2021 05:38] (current) – use wiki interwiki links Robin Getz
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 +====== DAQ2 HDL Project for Xilinx ======
  
-====== DAQ2 HDL Project for Xilinx====== +The reference design is a processor based embedded system. The sources are split into three different folders:
- +
-===== Xilinx block diagram ===== +
-{{:resources:eval:user-guides:ad-fmcdaq2-ebz:daq2_bd_v3.jpg?800|Xilinx HDL Block Diagram}} +
- +
- The reference design is a processor based embedded system. The sources are split between three different folders:+
   * base design for the carrier board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/common | /projects/common]] where all generic peripherals are instantiated. Here we do most of the PS8 configuration, add SPI, I2C and GPIOs. In some cases, we have scripts to instantiate also the PL DDR as ADC offload memory or DAC offload memory   * base design for the carrier board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/common | /projects/common]] where all generic peripherals are instantiated. Here we do most of the PS8 configuration, add SPI, I2C and GPIOs. In some cases, we have scripts to instantiate also the PL DDR as ADC offload memory or DAC offload memory
   * base design for the evaluation board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/common | /projects/daq2/common]], where all the IPs to control the DAQ2 evaluation board are instantiated, in a way in which it can be integrated with most of the carriers that we support   * base design for the evaluation board, [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/common | /projects/daq2/common]], where all the IPs to control the DAQ2 evaluation board are instantiated, in a way in which it can be integrated with most of the carriers that we support
-  * specific design for the project, in our case the ZCU102 [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/zcu102 | /projects/daq2/zcu102]]. Here, we source the carrier board configuration, then the evaluation board configuration and then we do some specific parameter modification, if required. In this folder, the constraints and system_top.v are also defined.+  * specific design for the project, in our case the ZCU102 [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/zcu102 | /projects/daq2/zcu102]]. Here, we source the carrier board configuration, then the evaluation board configuration and then we do some specific parameter modification, if required. In this folder, the constraints and ''system_top.v'' are also defined.
  
-The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface.+ 
 +==== AD-FMCDAQ2-EBZ block diagram ==== 
 +{{resources:eval:user-guides:ad-fmcdaq2-ebz:AD-FMCDAQ2-EBZ_1.svg?600|Xilinx HDL Block Diagram}} 
 + 
 +==== Xilinx block diagram ==== 
 +{{resources:eval:user-guides:ad-fmcdaq2-ebz:daq2_xilinx_2.svg?800|Xilinx HDL Block Diagram}} 
 + 
 + The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface.
  
 The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps, by default. The transceivers interface the ADC/DAC cores at 128bits@250MHz. The data is sent or received based on the configuration of separate transmit and receive chains. The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps, by default. The transceivers interface the ADC/DAC cores at 128bits@250MHz. The data is sent or received based on the configuration of separate transmit and receive chains.
  
-===== Project flow =====+===== Project Flow ===== 
 + 
 +The entry point for project creation is ''system_project.tcl''. Some support scripts are first loaded then the project is created. Based on the suffix of the project, the carrier board is automatically detected. The constraint files and custom modules instantiated directly in the system_top module must be added to the project files list.
  
-The entry point for project creation is system_project.tcl. Some support scripts are first loaded then the project is created. Based on the suffix of the project, the carrier board is automatically detected. The constraint files, and custom modules instantiated directly in the system_top module must be added to the project files list.+[[https://github.com/analogdevicesinc/hdl/blob/master/projects/daq2/zc706/system_project.tcl|system_project.tcl]] file:
  
 <code tcl> <code tcl>
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 </code> </code>
  
-When the project is created, system_bd.tcl is sourced. System_bd.tcl will generate the IP Integrator system. The resulting system will be instantiated in the system_top module.+When the project is created, ''system_bd.tcl'' is sourced. ''system_bd.tcl'' will generate the IP Integrator system. The resulting system will be instantiated in the system_top module.
  
 Some parameters will be defined in the first part, which will configure the ADC/DAC FIFOs. These are part of the systems in which the DDR throughput is not enough to keep up with the ADC/DAC data rates. Some parameters will be defined in the first part, which will configure the ADC/DAC FIFOs. These are part of the systems in which the DDR throughput is not enough to keep up with the ADC/DAC data rates.
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 </code> </code>
  
-The next step is to instantiate the ZCU102 base design: +The next step is to instantiate the ZCU102 base design: 
 <code tcl> <code tcl>
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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 If ADC/DAC FIFOs will be used in the system, the corresponding tcl files must be sourced. If ADC/DAC FIFOs will be used in the system, the corresponding tcl files must be sourced.
 +
 <code tcl> <code tcl>
 source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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 </code> </code>
  
-The next step is to source the DAQ2 specific design. +The next step is to source the DAQ2 specific design. 
 <code tcl> <code tcl>
 source ../common/daq2_bd.tcl source ../common/daq2_bd.tcl
 </code> </code>
  
-The generic design is optimized to supports the maximum number of carriers with minimal changes. If the specific carrier has different parameters than the default one, some minor IP parameter changes need to be done. In the case below, the generic design uses parameters for 7 Series FPGAs, so parameters must be adjusted for Ultrascale+.+The generic design is optimized to supports the maximum number of carriers with minimal changes. If the specific carrier has different parameters than the default, some minor IP parameter changes need to be done. In the case below, the generic design uses parameters for 7 Series FPGAs, so parameters must be adjusted for Ultrascale+.
  
 <code tcl> <code tcl>
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 ===== DAQ2 Design ===== ===== DAQ2 Design =====
  
-When using the JESD204 Framework, we source the JESD204 support script. In this script several procedures which simplify the design are defined:+When using the JESD204 Framework we need to source the JESD204 support script. In this script several procedures which simplify the design are defined:
  
 <code tcl> <code tcl>
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 </code> </code>
  
-==== Physical layer ====+==== Physical Layer ====
  
-The physical layer is responsible for instantiating and configuring the high speed serial transceivers in the FPGA. +The physical layer is responsible for instantiating and configuring the high speed serial transceivers in the FPGA.
 The physical layer is implemented with the use of two modules: AXI_ADXCVR and UTIL_ADXCVR. The physical layer is implemented with the use of two modules: AXI_ADXCVR and UTIL_ADXCVR.
-AXI_ADXCVR Provides an AXI interface for performing DRP reads and writes to the transceivers, allowing for dynamic reconfiguration.  +AXI_ADXCVR Provides an AXI interface for performing DRP reads and writes to the transceivers, allowing for dynamic reconfiguration. 
-Given that the hardware implements 4 data lines, that's how we'll configure the NUM_OF_LANES parameter.  +Given that the hardware implements 4 data lines, that's how we'll configure the NUM_OF_LANES parameter. 
-QPLL_ENABLE parameter gives control to this IP of the QPLL reconfiguration for the Transceiver QUAD. If the QUAD is shared with other RX IPs (as it is in this design), the second ADXCVR IP will need to have QPLL_ENALBE set to 0.+QPLL_ENABLE parameter gives control to this IP of the QPLL reconfiguration for the Transceiver QUAD. If the QUAD is shared with other RX IPs (as it is in this design), the second ADXCVR IP will need to have QPLL_ENABLE set to 0.
  
 <code tcl> <code tcl>
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 </code> </code>
  
-Instantiation of the ADC transceiver controller. For this IP, QPLL_ENABLE is set to 0. +Instantiation of the ADC transceiver controller. For this IP, QPLL_ENABLE is set to 0. 
 <code tcl> <code tcl>
 ad_ip_instance axi_adxcvr axi_ad9680_xcvr ad_ip_instance axi_adxcvr axi_ad9680_xcvr
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 </code> </code>
  
-Given that the IP uses the same QUAD as the DAC, when channel reconfiguration may affect the DAC and vice versa. When using the JESD204B framework, this is taken into consideration by software.+Given that the IP uses the same QUAD as the DAC, performing channel reconfiguration may affect the DAC and vice versa. When using the JESD204B framework, this is taken into consideration by software.
  
 The actual transceiver blocks are instantiated in UTIL_ADXCVR. The actual transceiver blocks are instantiated in UTIL_ADXCVR.
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 </code> </code>
  
-Xilinx JESD204-PHY IP can be used as an alternative to implement the physical layer, as it's part of Vivado without additional licensing. We don't currently provide software support for the Xilinx IP.+Xilinx JESD204-PHY IP can be used as an alternative to implementing the physical layer, as it's part of Vivado without additional licensing. We don't currently provide software support for the Xilinx IP. The drawback when using the Xilinx IP is that it doesn't provide Eyescan functionality.
  
 === Clocking === === Clocking ===
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 Reference clocks are needed to be feed to the QPLL/CPLL. In this design, we are using tx reference clock for QPLL and rx reference clock for QPLL. If the system works at 10Gbps, the QPLL clock will be used for both the RX and TX channels. Reference clocks are needed to be feed to the QPLL/CPLL. In this design, we are using tx reference clock for QPLL and rx reference clock for QPLL. If the system works at 10Gbps, the QPLL clock will be used for both the RX and TX channels.
 What is important to note is that the reference clocks for the transceiver QUAD must be connected to the MGTREFCLK pins either for the QUAD or an adjacent QUAD. What is important to note is that the reference clocks for the transceiver QUAD must be connected to the MGTREFCLK pins either for the QUAD or an adjacent QUAD.
 +
 <code tcl> <code tcl>
 create_bd_port -dir I tx_ref_clk_0 create_bd_port -dir I tx_ref_clk_0
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 ==== Data Link Layer ==== ==== Data Link Layer ====
  
-The JESD204 Data link layer is instantiated in the next lines, for TX and RX type of peripheral. +The JESD204 data link layer is instantiated in the next lines, for both TX and RX type of peripheral paths. 
-The ADI AD-IP-JESD204 implements the data link layer, supporting sublass 0 or subclass 1, runtime reconfigurability through an AXI memory mapped interface+The ADI AD-IP-JESD204 implements the data link layer, supporting subclass 0 or subclass 1 and runtime reconfigurability through an AXI memory mapped interface. 
 <code tcl> <code tcl>
 adi_axi_jesd204_tx_create axi_ad9144_jesd 4 adi_axi_jesd204_tx_create axi_ad9144_jesd 4
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 The IP is equivalent with the Xilinx licensed JESD204 IP. The IP is equivalent with the Xilinx licensed JESD204 IP.
  
-==== Transport layer ====+==== Transport Layer ==== 
 The transport layer peripherals are responsible for converter specific data framing and de-framing and provide a generic FIFO interface to the rest of the system. The transport layer peripherals are responsible for converter specific data framing and de-framing and provide a generic FIFO interface to the rest of the system.
  
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 ==== JESD204 Connections ==== ==== JESD204 Connections ====
 +
 When UTIL_ADXCVR is instantiated, the channel inside of the IP may be different than the hardware pin connection to lessen the layout burden. When UTIL_ADXCVR is instantiated, the channel inside of the IP may be different than the hardware pin connection to lessen the layout burden.
 Because of this, the UTIL_ADXCVR IP will rearrange the inside channels so that they correspond to the outside pin connection for the RX path, keeping a common transport layer. Because of this, the UTIL_ADXCVR IP will rearrange the inside channels so that they correspond to the outside pin connection for the RX path, keeping a common transport layer.
-Each channel from the QUAD has assigned a specific pin for TX and RX. After rearranging the channels so they correspond to the RX pins, the TX pins may not be in the order they are connected to the DAC. The below {0 2 3 1} parameter will connect the physical layer to the data link layer as if the channels and pin connections are in order. +Each channel from the QUAD has assigned a specific pin for TX and RX. After rearranging the channels so they correspond to the RX pins, the TX pins may not be in the order they are connected to the DAC. The below {0 2 3 1} parameter will connect the physical layer to the data link layer as if the channels and pin connections are in order.
  
 <code tcl> <code tcl>
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 ==== Additional IPs ==== ==== Additional IPs ====
-For a complete system, we use additional modules to transfer data. The transport layer transfers data continously from/to the ADC/DAC. CPACK/Upack will only send the enabled channels to the DMA which in turn will transfer it to the system memory. Depending on system specifics, data offload FIFOs may be inserted between upack/cpack and the DMA.+ 
 +For a complete system, we use additional modules to transfer data. The transport layer transfers data continuously from/to the ADC/DAC. CPACK/Upack will only send the enabled channels to the DMA which in turn will transfer it to the system memory. Depending on system specifics, data offload FIFOs may be inserted between upack/cpack and the DMA.
 When a FIFO is used, the DMA connection to the DDR can run at a lower speed, as data capture cannot be done continuously. When a FIFO is used, the DMA connection to the DDR can run at a lower speed, as data capture cannot be done continuously.
  
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 </code> </code>
  
-==== Misc connections ====+==== Misc Connections ==== 
 <code tcl> <code tcl>
 ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk ad_connect  util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
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 ==== CPU Address Allocation ==== ==== CPU Address Allocation ====
-The below instructions assign addresses to all AXI modules in the design.+ 
 +The below instructions assign addresses to all AXI modules in the design. These will be used when generating the device tree in linux. 
 <code tcl> <code tcl>
 # interconnect (cpu) # interconnect (cpu)
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 </code> </code>
  
-==== High perfomance port connections ==== +==== High Perfomance Port Connections ==== 
-The below instructions assign an HP port to all AXI masters, through an interconnect.  + 
-If there is a single master per interconnect, it will be bypassed in the interconnect. +The below instructions assign an HP port to all AXI masters, through an interconnect. 
 +If there is a single master per interconnect, it will be bypassed in the interconnect. 
 +The HP3 connections allow the physical layer to transmit eyescan data to memory, without software interference.
  
 <code tcl> <code tcl>
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 </code> </code>
  
-===== System top =====+===== System Top =====
  
-The reference clock that is used for the transceivers, must be captured by an IBUFDS_GTE4 block. Because UTIL_ADXCVR doesn't have the buffer instantiated, the best place to instantiate it is in system_top.v.+The reference clock that is used for the transceivers, must be captured by an IBUFDS_GTE4 block. Because UTIL_ADXCVR doesn't have the buffer instantiated, the best place to instantiate it is in ''system_top.v''.
  
 <code tcl> <code tcl>
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 As shown below, the transceiver channels and ADC channels are not connected one to one. As shown below, the transceiver channels and ADC channels are not connected one to one.
 +
 <code xdc> <code xdc>
 set_property  -dict {PACKAGE_PIN  K2} [get_ports rx_data_p[0]] ; ## A10  FMC_HPC0_DP3_M2C_P set_property  -dict {PACKAGE_PIN  K2} [get_ports rx_data_p[0]] ; ## A10  FMC_HPC0_DP3_M2C_P
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 </code> </code>
  
-The reference clocks run at 500 MHz, and the frame clock at 250, in the maximum throughput configuration, which is the default.+The reference clocks run at 500 MHz, and the frame clock at 250, in the maximum throughput configuration(default). 
 <code xdc> <code xdc>
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
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 create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK] create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
 </code> </code>
 +
 +===== Building the HDL Project =====
 +
 +When building the project, you should always use the recommended version of the tools for the specific [[/resources/fpga/docs/releases | release]]. In this example, we'll use release 2018_r1, which has Vivado 2017.4.1 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.
 +
 +<code>
 +mkdir adi
 +cd adi
 +git clone https://github.com/analogdevicesinc/hdl.git
 +cd hdl/
 +git status ## check for everything, including branch name
 +git checkout hdl_2018_r1 ## change to the hdl_2018_r2 branch
 +make -C projects/daq2/zcu102
 +</code>
 +
 +===== Building BOOT.BIN =====
 +
 +The boot image ''BOOT.BIN'' is build using the bootgen tool which requires several input files. For ease of use we provide a bash shell script which allows building ''BOOT.BIN'' from ''system_top.hdf'', ''u-boot.elf'' and either ''bl31.elf'' or a path to the Arm Trusted Firmware repository.
 +
 +The script can be downloaded from here:
 +
 +  * [[https://raw.githubusercontent.com/analogdevicesinc/wiki-scripts/master/zynqmp_boot_bin/build_zynqmp_boot_bin.sh|build_zynqmp_boot_bin.sh]]
 +
 +
 +**NOTE: After downloading the script you need to make it executable**\\
 +<xterm>
 +$ chmod +x build_zynqmp_boot_bin.sh
 +</xterm>
 +
 +<code>
 +usage: build_zynqmp_boot_bin.sh system_top.hdf u-boot.elf (download | bl31.elf | <path-to-arm-trusted-firmware-source>) [output-archive]
 +</code>
 +
 +  * Path to ''system_top.hdf'' and ''u-boot.elf'' are required parameters.
 +  * The 3rd argument must either be ''download'' (which will git clone the ATF repository), ''bl31.elf'' or the file system ''path'' to the Arm Trusted Firmware source code repository
 +  * An optionally 4th ''name'' parameter can be given to tar.gz the output directory. (''name''.tar.gz)
 +  * Build output is located in a local directory named: output_boot_bin.
 +  * This script requires Xilinx XSDK and bootgen in the PATH.\\
 +    * A simple way is to source vivado settings[32|64].sh:
 +
 +<code>
 +$ source /opt/Xilinx/Vivado/201x.x/settings64.sh
 +</code>
 +
 +**NOTE: u-boot.elf**\\
 +For those who don't want to build u-boot themselves.\\ 
 +The **u-boot.elf** can be extracted from the project folder on the [[resources/tools-software/linux-software/zynq_images#download_linux_image|SD Card image]], **bootgen_sysfiles.tgz** 
 +
 +===== References =====
 +
 +[[resources/fpga/docs/build|HDL Build Instructions]] \\
 +[[resources/tools-software/linux-software/build-the-zynqmp-boot-image|How to build the ZynqMP boot image BOOT.BIN]] \\
 +[[resources/tools-software/linux-software/build-the-zynq-boot-image|How to build the Zynq boot image BOOT.BIN]] \\
 +
resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx.1526386949.txt.gz · Last modified: 15 May 2018 14:22 by Adrian Costina

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