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resources:fpga:peripherals:jesd204:jesd204_troubleshooting [06 Feb 2020 16:52] – removed wraps Laszlo Nagyresources:fpga:peripherals:jesd204:jesd204_troubleshooting [20 Dec 2021 08:19] (current) – [Link status stays in CGS and SYNC~ is de-asserts] Laszlo Nagy
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-===== Troubleshooting JESD20B Tx/DAC links =====+===== Troubleshooting JESD204B Tx links =====
  
 Running one of the below commands on a Linux based system will return the status of the JESD link. Running one of the below commands on a Linux based system will return the status of the JESD link.
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 ==== Common symptoms ==== ==== Common symptoms ====
-Below table describes the most commonly occurred problems during link bring-up as solutions to overcome these in a Linux environment.+Below table describes the most commonly occurred problems during link bring-up and solutions to overcome these in a Linux environment.
  
  
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 </WRAP> </WRAP>
  
 +----
 +
 +====Link is DISABLED, In Linux boot log following appears:  axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 set lane rate 16500000 kHz failed (-22) ...====
 +<WRAP center round box 100%>
 +**Cause:** QPLL can't find a configuration for desired lane rate with the given reference clock.
 +
 +**Identify:** Check boot log. Check the required lane rate ref clock combination against the constraints defined in the transceiver manual.
 +
 +**Fix:** Configure the clock chip for different reference clock or switch to CPLL or QPLL0/1.
 +</WRAP>
 ---- ----
  
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   * OutClkSel - //adi,out-clk-select// device tree property from xcvr node   * OutClkSel - //adi,out-clk-select// device tree property from xcvr node
 </WRAP> </WRAP>
 +
 +----
 +
 +====Link status stays in CGS and SYNC~ is deasserted====
 +<WRAP center round box 100%>
 +**Cause:**  SYNC~ signal not connected correctly, pulled high
 +
 +**Identify:**  
 +#jesd_status
 +or
 +#grep "" /sys/bus/platform/devices/*.axi-jesd*/status*
 +  Link status: CGS
 +  SYNC~: deasserted
 +
 +**Fix:** Make sure SYNC~ is connected to the Link Transmit peripheral and is properly driven.
 +</WRAP>
 +
 +<WRAP center round box 100%>
 +**Cause:**  Receive endpoint of the JESD link is not up
 +
 +**Identify:**  
 +#jesd_status
 +or
 +#grep "" /sys/bus/platform/devices/*.axi-jesd*/status*
 +  Link status: CGS
 +  SYNC~: deasserted
 +
 +**Fix:** Make sure software communicates correctly with the DAC, bring-up sequence was executed and JESD RX blocks configured and enabled.
 +</WRAP>
 +
 +<WRAP center round box 100%>
 +**Cause:**  Missing SYSREF at peripheral in subclass 1
 +
 +**Identify:**  
 +#jesd_status
 +or
 +#grep "" /sys/bus/platform/devices/*.axi-jesd*/status*
 +  Link status: CGS
 +  SYNC~: deasserted
 +  SYSREF captured         No
 +
 +**Fix:** Make sure SYSREF is connected to the Link Transmit peripheral and is properly driven.
 +</WRAP>
 +
  
 ---- ----
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 ===== Support ===== ===== Support =====
-Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[https://ez.analog.com/community/fpga|EngineerZone]].+Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/fpga|EngineerZone]].
  
 ~~NOTOC~~ ~~NOTOC~~
  
resources/fpga/peripherals/jesd204/jesd204_troubleshooting.1581004377.txt.gz · Last modified: 06 Feb 2020 16:52 by Laszlo Nagy

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