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resources:fpga:peripherals:jesd204:axi_jesd204_rx [25 Aug 2022 17:55] Laszlo Nagy [64b/66b Link latency reduction] |
resources:fpga:peripherals:jesd204:axi_jesd204_rx [31 Aug 2022 11:18] Laszlo Nagy [64b/66b Link latency reduction] |
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| Once the slowest lane delay is identified, before enabling the links, SW needs to set the register ''BUFFER_DEALY'' (0x240) from all parallel Rx links if exists based on the following formula: | Once the slowest lane delay is identified, before enabling the links, SW needs to set the register ''BUFFER_DEALY'' (0x240) from all parallel Rx links if exists based on the following formula: | ||
| - | <m>Buffer Delay = (F*K - min(latency regs + 32)) / TPLDW + 4</m> | + | <m>Buffer Delay = (F*K - min(latency regs) + 32) / TPLDW + 4</m> |
| Where: | Where: | ||
resources/fpga/peripherals/jesd204/axi_jesd204_rx.txt · Last modified: 31 Aug 2022 11:18 by Laszlo Nagy