Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revisionLast revisionBoth sides next revision | ||
| resources:fpga:peripherals:jesd204:axi_jesd204_rx [25 Aug 2022 16:11] – [64b/66b Link latency reduction] Laszlo Nagy | resources:fpga:peripherals:jesd204:axi_jesd204_rx [31 Aug 2022 11:18] – [64b/66b Link latency reduction] Laszlo Nagy | ||
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| Line 469: | Line 469: | ||
| Once the slowest lane delay is identified, before enabling the links, SW needs to set the register '' | Once the slowest lane delay is identified, before enabling the links, SW needs to set the register '' | ||
| - | < | + | < |
| Where: | Where: | ||
| Line 477: | Line 477: | ||
| * TPLDW - TPL datapath width in octets. Can be read from the '' | * TPLDW - TPL datapath width in octets. Can be read from the '' | ||
| | | ||
| + | ** This value it the absolute minimum. It is recommended to increase it slightly to have a better margin against power-up to power-up latency variations.** | ||
resources/fpga/peripherals/jesd204/axi_jesd204_rx.txt · Last modified: 23 Jan 2024 10:40 by Adrian Costina