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--- resources:fpga:no-os_make:software_setup [13 Mar 2018 16:39] – created Andrei Grozav
+++ resources:fpga:no-os_make:software_setup [11 Aug 2021 20:20] (current) – Update HDF variable def for Xilinx Travis Collins
@@ Line 1: / Line 1: @@
-====== Command line build (automatic)======
+====== Build no-OS with GNU make ======
-Be sure you are using the latest release version and you have the corresponding branches for both hdl and no-Os([[https://github.com/analogdevicesinc/hdl/releases|Release notes]]).
+This guide provides some quick instructions on how to build and run the no-OS on almost all of the supported platforms.
-We strongly recommend to have a [[https://wiki.analog.com/resources/fpga/docs/git|clone]] of no-Os and hdl in the same folder:
+Be sure you are using the latest release version and you have the corresponding branches for both HDL and no-OS([[https://github.com/analogdevicesinc/hdl/releases|Release notes]]).
-  ~/github/hdl
-  ~/github/no-Os.
-The build flow is based on [[https://en.wikipedia.org/wiki/Make_(software)|make]].
+==== Building the HDL ====
-In every hdl based project one can find a folder with the supported carriers names. In each folder, there is a Makefile which points to the projects hdl (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.
+ADI does not distribute the bit/elf files of these projects. They must be built from the sources. The [[resources:fpga:docs:hdl|HDL User Guide]] provides detailed information and steps to build the HDL project on your desired carrier. The build flow is developed around [[https://www.gnu.org/software/make/|GNU make]]. You may use a Windows or Linux OS, but do NOT seek OS- specific support. The prerequisite to the building process is that you are able to run 'quartus', 'vivado' and 'make' all from a shell (Cygwin or Linux).
-===== Building the bare metal software =====
+Building the HDL is as simple as running make on your desired project and carrier.
-Do a
-  make
-in the carrier folder.
-\\
+<code>
+hdl/projects/daq3/kcu105> make
+hdl/projects/daq3/zc706> make
+</code>
- See [[:#particular_cases section|Particular cases]]
+<note important>
+For Intel nios2 based processor projects you have to turn off the MMU (Memory Management Unit used for Linux  OS) when building the HDL.
+</note>
+<code>
+hdl/projects/daq3/a10gx> make MMU=0
+</code>
-===== Running the bare metal software =====
+We strongly recommend having a [[/resources/fpga/docs/git|clone]] of no-Os and HDL in the same folder:
-  make run
+<code>
+  ~/github/hdl/
+  ~/github/no-OS/
+</code>
-The above command downloads the bitstream or the raw binary file on the FPGA than the elf file.
+In every project folder, you can find a separate subfolder for each supported carrier. In each carrier folder, there is a Makefile which points to the bit files and HDL deliverables (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.
-\\
-The software is started before the memory debugger disconnects
+===== Building the software =====
+Change your current directory to your targeted project and run make:
+<code>
+  [~] cd fmcdaq2/zc706
+  [~] make
+</code>
+See [[#troubleshooting| Troubleshooting]] section for guideline how to solve **make** related issues.
+===== Running the software =====
+Make sure that the FPGA is powered on and connected to the PC and then run the command:
+<code>
+  [~] make run
+</code>
+The **make run** will downloads the bitstream on the FPGA and after that program the board with the elf file.
+The software is started before the memory debugger disconnects.
 ===== Evaluating the result =====
-  make capture
-By default, the software captures (in case of ADC based projects) the data received from the device in the RAM.
+After the software has been run on the FPGA, run the command:
+<code>
+  [~] make capture
+</code>
+By default, the software captures (in case of ADC based projects) the data received from the device in the RAM.
+<code>
   rx_xfer.start_address = *_MEM_BASEADDR + OFFSET;
   rx_xfer.no_of_samples = value;
   dmac_start_transaction(ad_core_dma);
+</code>
 These values differ depending on the architecture and device.
@@ Line 46: / Line 76: @@
   * [[https://github.com/analogdevicesinc/no-OS/blob/master/scripts/zynq_u.mk#L15-L29|zynq_u]]
-For projects that have more than one channel or require a different number of capture samples one can specify this value in the projects common Makefile (ex: [[https://github.com/analogdevicesinc/no-OS/blob/master/fmcadc4/fmcadc4.mk#L15|fmcadc4]])
+The number of samples is specified in the project's common Makefile. (ex: [[https://github.com/analogdevicesinc/no-OS/blob/2019_R1/fmcadc4/fmcadc4.mk#L15|fmcadc4]])
 <note>The script will write a capture_chx.csv file for every channel.</note>
-<note>In the case of an RF device which has I and Q data for each channel. The number of capture_chx.csv will be double.</note>
+<note>In the case of an RF device which has I and Q data for each channel, the number of capture_chx.csv files will double.</note>
-For example in the case of fmcomms2(AD9361: 2RF channels)
+For example, for fmcomms2(AD9361: 2RF channels):
 ^fmcomms2                                    ^^^
@@ Line 61: / Line 91: @@
 ===== Clean the workspace =====
+<code>
+  [~] make clean
+</code>
+===== Troubleshooting =====
-  make clean
+<code>
-===== Particular cases=====
-If you get
   make: *** No rule to make target `../../../hdl/projects/daq2/vc707/daq2_vc707.sdk/system_top.hdf', needed by `hw/system_top.bit'.  Stop.
+</code>
-Your hdl in not build or the folder structure is not the one recommended at the beginning of this page, you have to build/specify hdl location.
-  * [[https://wiki.analog.com/resources/fpga/docs/build|Build]]
+The HDL deliverables cannot be found. Maybe the targeted HDL project is not built, or the defined path is not valid. Make sure, that you build the HDL before running the no-OS or specify the location of the HDL deliverables explicitly.
-  * Specify hdl location:
+  * [[resources/fpga/docs/build|Build]]
+  * Specify HDL location:
 For Xilinx
-  make M_HDF_FILE=<HDL-REPO>/projects/my_project/carrier/*.sdk/system_top.hdf
+<code>
+  [~] make HARDWARE=/<path_to_hdf>/system_top.hdf
+</code>
 For Intel
-  make M_SOPCINFO_FILE=<HDL-repo>/projects/my_project/carrier/system_bd.sopcinfo M_SOF_FILE=my_project_carrier.sof
+<code>
+  [~] make M_SOPCINFO_FILE=/<path_to_sopcinfo>/system_bd.sopcinfo
+</code>
+===== Understanding/Modifying things =====
+The best place to start in the no-OS main function in "project/project_name.c". It shows how individual components of a data path chain are initialized and programmed for the application. After you have the default setup working, feel free to add your own customization routines and/or signal processing functions to either HDL or no-OS.
-  make run (plus the above)
+{{navigation Build no-OS with GNU make#resources:fpga:xilinx:software_setup|Xilinx SDK GUI#resources:fpga:quick_validation|Quick validation#resources:fpga:uart_setup|UART setup}}

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