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This version is outdated by a newer approved version.DiffThis version (13 Mar 2018 16:39) is a draft.
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Table of Contents

Command line build (automatic)

Be sure you are using the latest release version and you have the corresponding branches for both hdl and no-Os(Release notes).

We strongly recommend to have a clone of no-Os and hdl in the same folder: 

~/github/hdl
~/github/no-Os.

The build flow is based on make.

In every hdl based project one can find a folder with the supported carriers names. In each folder, there is a Makefile which points to the projects hdl (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.

Building the bare metal software

Do a 

make

in the carrier folder.

See Particular cases

Running the bare metal software

make run

The above command downloads the bitstream or the raw binary file on the FPGA than the elf file.
The software is started before the memory debugger disconnects

Evaluating the result

make capture

By default, the software captures (in case of ADC based projects) the data received from the device in the RAM. 

rx_xfer.start_address = *_MEM_BASEADDR + OFFSET;
rx_xfer.no_of_samples = value;
dmac_start_transaction(ad_core_dma);

These values differ depending on the architecture and device.

The Makefiles have these parameters initialized with default values:

For projects that have more than one channel or require a different number of capture samples one can specify this value in the projects common Makefile (ex: fmcadc4)

The script will write a capture_chx.csv file for every channel.
In the case of an RF device which has I and Q data for each channel. The number of capture_chx.csv will be double.

For example in the case of fmcomms2(AD9361: 2RF channels)

fmcomms2
channel1 data I capture_ch1.csv
data Q capture_ch2.csv
channel2 data I capture_ch3.csv
data Q capture_ch4.csv

Clean the workspace

make clean

Particular cases

If you get 

make: *** No rule to make target `../../../hdl/projects/daq2/vc707/daq2_vc707.sdk/system_top.hdf', needed by `hw/system_top.bit'.  Stop.

Your hdl in not build or the folder structure is not the one recommended at the beginning of this page, you have to build/specify hdl location.

  • Specify hdl location:

For Xilinx 

make M_HDF_FILE=<HDL-REPO>/projects/my_project/carrier/*.sdk/system_top.hdf

For Intel 

make M_SOPCINFO_FILE=<HDL-repo>/projects/my_project/carrier/system_bd.sopcinfo M_SOF_FILE=my_project_carrier.sof
make run (plus the above)
resources/fpga/no-os_make/software_setup.1520955565.txt.gz · Last modified: 13 Mar 2018 16:39 by Andrei Grozav

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