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This version (21 Feb 2019 15:31) was approved by Istvan Csomortani.
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Table of Contents
Xilinx FPGAs Transceivers Wizard
The 7 Series and Ultrascale FPGAs Transceivers Wizard can be used to configure the transceivers inside the util_adxcvr core. In general in all reference designs the gigabit transceivers are configured to the highest supported line rate of the device. If the user wants to use their system with a different line rate, she needs to reconfigure the transceivers. This can be done by software, which does the reconfiguration through the DRP interface of the transceivers. Due the complexity of the transceivers, it can happen that the user needs to do addition settings in HDL using the Wizard. The following wiki provides a short guide on how to use the wizard to generate a transceiver configuration for a JESD204B interface.
Required features by the JESD204B
The following features are required for a JESD204B interface:
- QPLL and CPLL for clock generation
- 8B/10B encoding and decoding
- TX and RX buffer to solve rate and phase differences between XCLK (PMA parallel clock) and USRCLK (device clock)
- RX Equalization and CDR
- RX Byte and Word alignment
- Tx configurable driver
- Polarity control
7 Series FPGAs Transceiver Wizard
To start the wizard in the Vivado, a project should be loaded with a 7 Series FPGA which has gigabit transceivers. In the Project Manager select IP catalog and search after the keyword wizard, then select the 7 Series FPGAs Transceivers Wizard IP.
You can define a custom name for your component and leave it on default. The tools should recognize your transceiver type automatically, if not, you may have to double check if you have the right FPGA device selected for your project. You also need to select Include Shared Logic in core at the Shared Logic section in order to have both COMMON and CHANNEL instances in the generated code.
Line Rate and RefClk Selection
First, you need to select JESD204 as targeted protocol and specify your line rate and reference clock. A valid reference clock depends on your line rate. Make sure that you're using a valid reference clock form the drop-down list. Also you should set the used PLLs for TX and RX. If your line rate is equal for both directions, you can use the same PLL. Be aware that each PLL's VCO has a different frequency range where the circuit can function correctly. If your targeted line rate is too high or too low, you may be restricted to use just one of the two PLLs. All other settings can be left on their default value in this tab.
Encoding and Clocking
If you selected JESD204 to be the used protocol, you don't have to change anything here. The JESD204B interface is using 8B/10B encoding/decoding, and the internal data width will be 40 bits. In all the reference designs the DRP frequency is connected to the system clock (100 MHz). In the Synchronization and Clocking section, both TX and RX should have an enabled buffer. The PLLREFCLK is used as the source for TXOUTCLK and RXOUTCLK.
Other tabs
The setting from the tabs PCIe, SATA, PRBS and CB and CC Sequence can be left to their default values.
Generated files
Location of the COMMON instance: <project_name>/<project_name>.srcs/sources_1/ip/<component_name>/<component_name>_common.v Location of the CHANNEL instance: <project_name>/<project_name>.srcs/sources_1/ip/<component_name>/<component_name>_gt.v
[~] less daq2_zc706.srcs/sources_1/ip/gtwizard_0/gtwizard_0_common.v [~] less daq2_zc706.srcs/sources_1/ip/gtwizard_0/gtwizard_0_gt.v
This instances should be compared with the COMMON and CHANNEL instances used in util_adxcvr_cm.v and util_adxcvr_ch.v.
Ultrascale and Ultrascale+ FPGAs Transceiver Wizard
The overall workflow with the Ultrascale FPGAs Transceiver Wizard is similar to the 7 Series one, it just has a different GUI. To open up the wizard in the Project Manager select IP Catalog and search after the keyword wizard, then select the Ultrascale FPGAs Transceivers Wizard. You can define a custom name for your component and leave it on default. The tools should recognize your transceiver type automatically, if not, you may have to double check if you have the right FPGA device selected for your project. To apply the general JESD204B setting, select the GTH-JESD204 preset. In the first tab, called Basic you can find all the necessary settings. Select the targeted line rate, PLL and reference clock. The tool will tell you what PLL and reference clock can be used with a specific line rate. Note that the current version of the util_adxcvr core does not support QPLL Fractional-N option.
To have both COMMON and CHANNEL instances inside the generated core, in the Structural Options tab the Include transceiver COMMON in the Core option must be selected.
Generated files
To find the actual instance attributes, two different files should be examined. A generic one, which contains the actual software macro instance, and a wrapper, which instanciates the previous file and sets the required attributes.
Location of the COMMON instance: <project_name>/<project_name>.srcs/sources_1/ip/<component_name>/synth/gtwizard_ultrascale_v1_7_gthe4_common.v
Location of the COMMON wrapper: <project_name>/<project_name>.srcs/sources_1/ip/<component_name>/synth/<component_name>_gthe4_common_wrapper.v
Location of the CHANNEL instance: <project_name>/<project_name>.srcs/sources_1/ip/<component_name>/synth/gtwizard_ultrascale_v1_7_gthe4_channel.v
Location of the CHANNEL instance: <project_name>/<project_name>.srcs/sources_1/ip/<component_name>/synth/<component_name>_gthe4_channel_wrapper.v
[~] less daq2_zcu102.srcs/sources_1/ip/gth_jesd204/synth/gtwizard_ultrascale_v1_7_gthe4_common.v [~] less daq2_zcu102.srcs/sources_1/ip/gth_jesd204/synth/gth_jesd204_gthe4_common_wrapper.v [~] less daq2_zcu102.srcs/sources_1/ip/gth_jesd204/synth/gtwizard_ultrascale_v1_7_gthe4_channel.v [~] less daq2_zcu102.srcs/sources_1/ip/gth_jesd204/synth/gth_jesd204_gthe4_channel_wrapper.v
The example above is for the project DAQ2 with ZCU102 and with a component name of gth_jesd204.
This generated attributes values should be compared with the values used with the COMMON and CHANNEL instances in util_adxcvr_cm.v and util_adxcvr_ch.v.
resources/fpga/docs/xgt_wizard.1550753168.txt.gz · Last modified: 21 Feb 2019 13:46 by Adrian Costina