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resources:fpga:docs:util_xcvr [13 Oct 2021 08:56]
Iulia Moldovan Edit footer
resources:fpga:docs:util_xcvr [08 Dec 2021 11:03]
Laszlo Nagy [Design Guidelines]
Line 88: Line 88:
  
 For porting on different Xilinx transceiver types, there is the following [[.:​xgt_wizard|guide]]. ​ For porting on different Xilinx transceiver types, there is the following [[.:​xgt_wizard|guide]]. ​
 +
 +==== Physical constraints considerations ====
 +
 +the util_adxcvr allocates resources/​quads (channels and common) sequentially. ​ Meaning if you have 8 lanes, ​ it will insert two quads, ​ 4 channels and a common block for each quad.
 +
 +Channels within a quad are tightly coupled to the common block, the placement of the channel resources can be permuted within a quad and is affected by the constraint file  with the restriction that rx_<​N>​_p/​n connect to tx_<​N>​_p/​n must connect to the same channel.
 +
 +Supposing we have the following pin constraints and connections to the util_adxcvr:​
 +{{ :​resources:​fpga:​docs:​xcvr_mapping_example.jpg?​nolink |}}
 +
 +So in this case we end up with a conflict during implementation:​
 +{{ :​resources:​fpga:​docs:​xcvr_conflict.jpg?​nolink |}}
 +We have to ensure that in implementation the mapping is correct either by rearranging the Rx connections.
 +{{ :​resources:​fpga:​docs:​xcvr_rx_rearrangement.jpg?​nolink |}}
 +or the Tx connections of the util_adxcvr
 +{{ :​resources:​fpga:​docs:​xcvr_tx_rearrangement.jpg?​nolink |}}
 +
 +In such cases when rearrangement is required due placement constraints,​ complementary reordering is required either in the converter device (lane crossbars) or inside the FPGA between the physical and link layer to connect the logical lanes with the same index on both end of the link.
 +
  
  
resources/fpga/docs/util_xcvr.txt · Last modified: 08 Dec 2021 11:03 by Laszlo Nagy