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resources:fpga:docs:util_var_fifo [23 May 2017 10:55] – created Adrian Costinaresources:fpga:docs:util_var_fifo [13 Oct 2021 08:37] (current) – Edit footer Iulia Moldovan
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-===== UTIL_VAR_FIFO =====+====== UTIL_VAR_FIFO ======
  
 The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering. The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering.
  
-==== Features ====+ 
 +===== Features =====
  
   * Variable depth   * Variable depth
  
-==== Configuration Parameters ====+ 
 +===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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 | ''ADDRESS_WIDTH'' | The BRAM generator parameters should match this. Gives the maximum depth of the FIFO | 13 | | ''ADDRESS_WIDTH'' | The BRAM generator parameters should match this. Gives the maximum depth of the FIFO | 13 |
  
-==== Interface ====+ 
 +===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 | ** Data Input**  |||| | ** Data Input**  ||||
 |              | ''data_in'' | ''input[DATA_WIDTH-1:0]'' | Data to be stored | |              | ''data_in'' | ''input[DATA_WIDTH-1:0]'' | Data to be stored |
-|              | ''data_in_valid'' | ''input[15:0]'' | Valid for the input data |+|              | ''data_in_valid'' | ''input'' | Valid for the input data |
 | ** Data Output**  |||| | ** Data Output**  ||||
 |              | ''data_out'' | ''output[DATA_WIDTH-1:0]'' | Data forwarded to the DMA | |              | ''data_out'' | ''output[DATA_WIDTH-1:0]'' | Data forwarded to the DMA |
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 | **BRAM Connections** | ||| | **BRAM Connections** | |||
 |              | ''wea_w'' | ''output'' | Write signal | |              | ''wea_w'' | ''output'' | Write signal |
-|              | ''en_w'' | ''output'' |  Write enable signal | +|              | ''en_w'' | ''output'' | Write enable signal | 
-|              | ''addr_w'' | ''output[ADDRESS_WIDTH-1:0]'' | Address to the write pointer |+|              | ''addr_w'' | ''output[ADDRESS_WIDTH-1:0]'' | Address for the write pointer |
 |              | ''din_w'' | ''output[DATA_WIDTH-1:0]'' | Data to be written to the BRAM | |              | ''din_w'' | ''output[DATA_WIDTH-1:0]'' | Data to be written to the BRAM |
 |              | ''en_r'' | ''output'' | Read enable signal | |              | ''en_r'' | ''output'' | Read enable signal |
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 |              | ''dout_r'' | ''input[DATA_WIDTH-1:0]'' | Data read from the BRAM | |              | ''dout_r'' | ''input[DATA_WIDTH-1:0]'' | Data read from the BRAM |
  
-==== Detailed Description ==== 
  
-This IP controlls and external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.+===== Detailed Description ===== 
 + 
 +This IP controls an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two. 
 + 
 + 
 +===== Design Guidelines =====
  
-==== Design Guidelines ====+The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It uses only one clock domain, so everything should be synchonous to that clock domain.
  
-The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It only one clock domain, so everything should be synchonous to that clock domain. 
  
-==== References ==== +===== References ===== 
-  * [[https://github.com/analogdevicesinc/hdl/tree/dev/library/util_var_fifo| UTIL_VAR_FIFO IP source code]] \\ +  * [[https://github.com/analogdevicesinc/hdl/tree/master/library/util_var_fifo| UTIL_VAR_FIFO IP source code]] \\ 
-  * [[https://wiki.analog.com/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\+  * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\
  
-{{navigation #axi_ip|AXI IP#hdl_2_0|Main page#util_ip|UTIL IP Cores}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/util_var_fifo.1495529736.txt.gz · Last modified: 23 May 2017 10:55 by Adrian Costina

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