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resources:fpga:docs:util_var_fifo [11 Oct 2021 14:56] – Edit footer Iulia Moldovanresources:fpga:docs:util_var_fifo [13 Oct 2021 08:37] (current) – Edit footer Iulia Moldovan
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-===== UTIL_VAR_FIFO =====+====== UTIL_VAR_FIFO ======
  
 The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering. The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering.
  
-==== Features ====+ 
 +===== Features =====
  
   * Variable depth   * Variable depth
  
-==== Configuration Parameters ====+ 
 +===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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 | ''ADDRESS_WIDTH'' | The BRAM generator parameters should match this. Gives the maximum depth of the FIFO | 13 | | ''ADDRESS_WIDTH'' | The BRAM generator parameters should match this. Gives the maximum depth of the FIFO | 13 |
  
-==== Interface ====+ 
 +===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 |              | ''dout_r'' | ''input[DATA_WIDTH-1:0]'' | Data read from the BRAM | |              | ''dout_r'' | ''input[DATA_WIDTH-1:0]'' | Data read from the BRAM |
  
-==== Detailed Description ====+ 
 +===== Detailed Description =====
  
 This IP controls an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two. This IP controls an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.
  
-==== Design Guidelines ====+ 
 +===== Design Guidelines =====
  
 The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It uses only one clock domain, so everything should be synchonous to that clock domain. The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It uses only one clock domain, so everything should be synchonous to that clock domain.
  
-==== References ====+ 
 +===== References =====
   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/util_var_fifo| UTIL_VAR_FIFO IP source code]] \\   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/util_var_fifo| UTIL_VAR_FIFO IP source code]] \\
   * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\   * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\
  
-{{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/util_var_fifo.txt · Last modified: 13 Oct 2021 08:37 by Iulia Moldovan