The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering.
| ||Data width of the FIFO. The BRAM generator parameters should match this||32|
| ||The BRAM generator parameters should match this. Gives the maximum depth of the FIFO||13|
| || ||Clock input. Should be synchronous to the input and the output data|
| || ||Reset input. Should be synchronous clk clock|
| || ||Controls the depth of the FIFO. Should be less than the maximum depth. Controlled by an outside IP|
| || ||Data to be stored|
| || ||Valid for the input data|
| || ||Data forwarded to the DMA|
| || ||Valid for the output data|
| || ||Write signal|
| || ||Write enable signal|
| || ||Address for the write pointer|
| || ||Data to be written to the BRAM|
| || ||Read enable signal|
| || ||Address for the read pointer|
| || ||Data read from the BRAM|
This IP controls an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.
The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It uses only one clock domain, so everything should be synchonous to that clock domain.