This version (13 Oct 2021 10:46) was approved by Adrian Costina.The Previously approved version (11 Oct 2021 14:56) is available.Diff


The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering.


  • Variable depth

Configuration Parameters

Name Description Default Value
DATA_WIDTH Data width of the FIFO. The BRAM generator parameters should match this 32
ADDRESS_WIDTH The BRAM generator parameters should match this. Gives the maximum depth of the FIFO 13


Interface Pin Type Description
clk input Clock input. Should be synchronous to the input and the output data
rst input Reset input. Should be synchronous clk clock
depth input[31:0] Controls the depth of the FIFO. Should be less than the maximum depth. Controlled by an outside IP
Data Input
data_in input[DATA_WIDTH-1:0] Data to be stored
data_in_valid input Valid for the input data
Data Output
data_out output[DATA_WIDTH-1:0] Data forwarded to the DMA
data_out_valid output Valid for the output data
BRAM Connections
wea_w output Write signal
en_w output Write enable signal
addr_w output[ADDRESS_WIDTH-1:0] Address for the write pointer
din_w output[DATA_WIDTH-1:0] Data to be written to the BRAM
en_r output Read enable signal
addr_r output[ADDRESS_WIDTH-1:0] Address for the read pointer
dout_r input[DATA_WIDTH-1:0] Data read from the BRAM

Detailed Description

This IP controls an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.

Design Guidelines

The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It uses only one clock domain, so everything should be synchonous to that clock domain.


resources/fpga/docs/util_var_fifo.txt · Last modified: 13 Oct 2021 08:37 by Iulia Moldovan