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resources:fpga:docs:util_upack [11 Oct 2021 14:55] – Edit next page to be Using and modifying the HDL design Iulia Moldovanresources:fpga:docs:util_upack [13 Oct 2021 08:34] (current) – Edit footer & title Iulia Moldovan
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-====== Channel UNPACK Utility Core  (util_upack) ======+====== Channel UNPACK Utility Core ====== 
 + 
 +The channel UNPACK utility core (util_upack) is meant to allow one or more channels to be enabled by software without any padding. This allows full usage of the DMA bandwidth without any overhead. This core is normally works with the DAC and DMA modules. The DAC interface is channel based (one interface per each DAC channel) and consists of enable, valid and data signals. The DMA interface is a single FIFO interface consisting of valid and data signals. The enable signals are usually controlled by software. The core simply unpacks the DMA data into the individual channels as defined by the enables.
  
-The channel UNPACK utility core is meant to allow one or more channels to be enabled by software without any padding. This allows full usage of the DMA bandwidth without any overhead. This core is normally works with the DAC and DMA modules. The DAC interface is channel based (one interface per each DAC channel) and consists of enable, valid and data signals. The DMA interface is a single FIFO interface consisting of valid and data signals. The enable signals are usually controlled by software. The core simply unpacks the DMA data into the individual channels as defined by the enables. 
  
 ===== Features ===== ===== Features =====
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   * Supports up to 8 channels   * Supports up to 8 channels
   * Supports configurable channel data width   * Supports configurable channel data width
 +
  
 ===== Functional Description ===== ===== Functional Description =====
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 This data unpacking now needs to factor in the valid and the number of samples that are to be read from the DMA. It is quite simple a valid at the DAC interface translates into a data required count based on the number of enables. So if three channels are enabled the requirement is 6 samples, so the core initiates a read from the DMA three out of four clock cycles. This data unpacking now needs to factor in the valid and the number of samples that are to be read from the DMA. It is quite simple a valid at the DAC interface translates into a data required count based on the number of enables. So if three channels are enabled the requirement is 6 samples, so the core initiates a read from the DMA three out of four clock cycles.
 +
 +
 ===== Parameters ===== ===== Parameters =====
  
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 | ''CHANNEL_DATA_WIDTH'' | Data width of a channel | 32 | | ''CHANNEL_DATA_WIDTH'' | Data width of a channel | 32 |
 | ''NUM_OF_CHANNELS'' | Number of channels, max value is 8 | 8 | | ''NUM_OF_CHANNELS'' | Number of channels, max value is 8 | 8 |
 +
  
 ===== Interface ===== ===== Interface =====
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 | '' dma_xfer_in '' | input | XFER_REQ from DMA, indicates an active DMA transfer | | '' dma_xfer_in '' | input | XFER_REQ from DMA, indicates an active DMA transfer |
 | '' dac_xfer_out '' | output | XFER_REQ to DAC, forwarded xfer request | | '' dac_xfer_out '' | output | XFER_REQ to DAC, forwarded xfer request |
 +
  
 ===== Register Map ===== ===== Register Map =====
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 This core does not have a register map. This core does not have a register map.
  
-{{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/util_upack.txt · Last modified: 13 Oct 2021 08:34 by Iulia Moldovan