This version is outdated by a newer approved version.
This version (06 Jun 2018 13:00) was approved by Adrian Costina.
This version (06 Jun 2018 13:00) was approved by Adrian Costina.This is an old revision of the document!
Table of Contents
UTIL_EXTRACT
The UTIL_EXTRACT IP allows the extraction of the trigger signal and restoration of the data signal that was embedded in the data stream by the AXI_ADC_TRIGGER IP.
Configuration Parameters
| Name | Description | Default Value |
|---|---|---|
NUM_OF_CHANNELS | Number of channels | 2 |
DATA_WIDTH | Data width. It assumes the trigger is in bit (n*16)-1, with n being the channel number | NUM_OF_CHANNELS * 16 |
Interface
| Interface | Pin | Type | Description |
|---|---|---|---|
| Clock | |||
clk | input | Clock input. Should be synchronous to the input and the output data | |
| Data Input | |||
data_in | input[DATA_WIDTH-1:0] | Input data from the FIFO. Will replace each trigger bit with the sign extended version of the data. It should be data from the output of the variable fifo | |
data_in_trigger | input[DATA_WIDTH-1:0] | Data from which the trigger is extracted. It should be data from the input of the variable fifo | |
data_in_valid | input | Valid for the input data | |
| Data Output | |||
data_out | output[DATA_WIDTH-1:0] | Data without the embedded trigger | |
trigger_out | output | Trigger output. Is an logic OR of the triggers from all the channels that are captured simulaneously | |
References
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resources/fpga/docs/util_extract.1528282814.txt.gz · Last modified: 06 Jun 2018 13:00 by Adrian Costina