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FMCOMMS11 HDL Reference Design
Introduction to boards based on the AD9361/AD9363/AD9364
AD_QUADMXFE1_EBZ HDL Reference Design
AXI_AD777x
AXI_AD7768
AXI_ADAQ8092
Avalon Transceiver Configuration Core (avl_adxcfg)
Avalon Transceiver Core
AXI_AD3552R
AXI_AD4858
AXI_AD7606x
AXI_AD7616
AXI_AD9144 (Obsolete)
AXI_AD9265
AXI_AD9361
AXI_AD9371 (Obsolete)
AXI_AD9467
AXI_AD9643 (Obsolete)
AXI_AD9671
AXI_AD9783
AXI_AD9963
AXI_ADC_DECIMATE
Generic AXI ADC IP core
AXI_ADC_TRIGGER
AXI_ADXCVR
AXI CLKGEN IP core
AXI_DAC_INTERPOLATE
Generic AXI DAC IP core
High-Speed DMA Controller Peripheral
AXI Fan Control IP Core
AXI_HDMI_RX IP core
AXI_HDMI_TX IP core
AXI Laser Driver IP core
AXI_LOGIC_ANALYZER
AXI_LTC235x IP core
AXI_LTC2387
AXI_PWM_GEN
System ID
Generic Time-Division Duplexing Controller
Data Offload Engine HDL IP Core
Direct digital synthesis
ADI™ Reference Designs HDL User Guide
Creating a new IP
Use ADI IPs into your own project
ADI IP cores
Third-party repositories
AXI Stream FIFO Core
Asymmetric AXI Stream FIFO Core
Channel CPACK Utility Core
UTIL_EXTRACT
UTIL_MII_TO_RMII
UTIL_RFIFO
Channel UNPACK Utility Core
UTIL_VAR_FIFO
UTIL_ADXCVR core for Xilinx devices
JESD204B/C Link Receive Peripheral
SPI Engine
AXI SPI Engine FPGA Peripheral
Playing with xsdb
Quick system validation with no-Os
resources/fpga/docs/tips.txt
· Last modified: 12 May 2022 14:54 by
Liviu-Mihai Iacob
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