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This version (12 Jun 2019 10:37) was approved by AdrianC.The Previously approved version (09 Jan 2019 13:53) is available.Diff

Releases

The HDL is released as git branches bi-annually. The release branches are created first and then tested before being made official. That is, the existence of a branch does not mean it is a fully tested release. Also, the release branch is tested ONLY on certain versions of the tools and may NOT work with other versions of the tools. The projects that are tested and supported in a release branch are listed here along with the ADI library cores that are used. The branch may contain other projects that are in development, one must assume these are NOT tested and therefore NOT supported by this release.

Porting a release branch to another Tool version

It is possible to port a release branch to another tool version, though not recommended. The ADI libraries should work across different versions of the tools, but the projects may not. The issues are most likely with the Altera and Xilinx cores. If you must still do this, note the following:

First, disable the version check of the scripts.

The ADI build scripts are making sure that the releases are being run on the validated tool version. It will promptly notify the user if he or she trying to use an unsupported version of tools. You need to disable this check by setting the environment variable ADI_IGNORE_VERSION_CHECK.

Second, make Altera and Xilinx IP cores version changes.

The Altera projects should automatically be changed by Quartus. The Xilinx projects are a bit tricky. The GUI automatically updates the cores, but the TCL flow does NOT. So it may be easier to create the project file with the supported version first, then opening it with the new version. After which, update the TCL scripts accordingly.

The versions are specified in the following format.

add_instance sys_cpu altera_nios2_gen2 16.0 
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb] 

You should now be able to build the design and test things out. In most cases, it should work without much effort. If it doesn't do an incremental update and debug accordingly.

Release Branches

Releases Altera Xilinx Release Notes List of Supported Projects and IP cores
master Quartus 18.1 Vivado 2018.3 Release Notes master
hdl_2018_r2 Quartus 18.0 Vivado 2018.2 Release Notes 2018_r2
hdl_2018_r1 Quartus 17.1.1 Vivado 2017.4.1 Release Notes 2018_r1
hdl_2017_r1 Quartus 16.1 Vivado 2016.4 Release Notes 2017_r1
hdl_2016_r2 Quartus 16.0 Vivado 2016.2 Release Notes 2016_r2
hdl_2016_r1 Quartus 15.1 Vivado 2015.4.2 Release Notes 2016_r1
hdl_2015_r2 Quartus 15.0.2 Vivado 2015.2 Release Notes 2015_r2
hdl_2015_r1 Quartus 14.1 Vivado 2014.4.1 Release Notes 2015_r1
hdl_2014_r2 Quartus 14.0 Vivado 2014.2 Release Notes 2014_r2
hdl_2014_r1 Quartus 14.0 Vivado 2013.4 Release Notes 2014_r1

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resources/fpga/docs/releases.txt · Last modified: 12 Jun 2019 10:37 by AdrianC