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resources:fpga:docs:hdl:utilization_master [20 Jul 2022 13:48] – Update to current designs Stanca-Florina Popresources:fpga:docs:hdl:utilization_master [23 Sep 2022 14:12] – Update using 2022.09.21 log artifacts Stanca-Florina Pop
Line 6: Line 6:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6325, (11.89%) |7834, (7.36%) |9, (17.31%) |6.5, (4.09%) |4.37 |0 |0 | +| 6333, (11.90%) |7834, (7.36%) |9, (16.82%) |6.5, (4.09%) |4.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad4630_fmc_zed ==== ==== ad4630_fmc_zed ====
Line 12: Line 12:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6855, (12.89%) |9573, (9.00%) |9, (17.99%) |6.5, (4.09%) |4.37 |0 |0 | +| 6839, (12.86%) |9573, (9.00%) |9, (17.54%) |6.5, (4.09%) |4.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad469x_fmc_zed ==== ==== ad469x_fmc_zed ====
Line 18: Line 18:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6583, (12.37%) |8644, (8.12%) |9, (17.54%) |6.5, (4.09%) |4.37 |0 |0 | +| 6574, (12.36%) |8644, (8.12%) |9, (17.11%) |6.5, (4.09%) |4.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad5758_sdz_zed ==== ==== ad5758_sdz_zed ====
Line 24: Line 24:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 4126, (7.76%) |5195, (4.88%) |9, (17.16%) |2, (4.09%) |2.76 |0 |0 | +| 4108, (7.72%) |5195, (4.88%) |9, (16.35%) |2, (4.09%) |2.76 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad5766_sdz_zed ==== ==== ad5766_sdz_zed ====
Line 30: Line 30:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6349, (11.93%) |7982, (7.50%) |9, (16.28%) |3, (4.09%) |3.12 |0 |0 | +| 6338, (11.91%) |7982, (7.50%) |9, (15.74%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad6676evb_vc707 ==== ==== ad6676evb_vc707 ====
Line 36: Line 36:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 42377, (13.96%) |49507, (8.15%) |4, (14.82%) |148, (0.14%) |7.25 |0 |1 | +| 42391, (13.96%) |49500, (8.15%) |4, (14.79%) |148, (0.14%) |7.25 |0 |1 | 
 </WRAP> </WRAP>
 ==== ad6676evb_zc706 ==== ==== ad6676evb_zc706 ====
Line 42: Line 42:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 9372, (4.29%) |11447, (2.62%) |9, (19.54%) |3, (1.00%) |0.78 |0 |0 | +| 9336, (4.27%) |11446, (2.62%) |9, (19.37%) |3, (1.00%) |0.78 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad7134_fmc_zed ==== ==== ad7134_fmc_zed ====
Line 48: Line 48:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 7253, (13.63%) |9828, (9.24%) |9, (16.20%) |8.5, (4.09%) |5.08 |0 |0 | +| 7244, (13.62%) |9828, (9.24%) |9, (15.78%) |8.5, (4.09%) |5.08 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad738x_fmc_zed ==== ==== ad738x_fmc_zed ====
Line 54: Line 54:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6116, (11.50%) |7357, (6.91%) |9, (16.87%) |3, (4.09%) |3.12 |0 |0 | +| 6102, (11.47%) |7356, (6.91%) |9, (16.39%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad7405_fmc_zed ==== ==== ad7405_fmc_zed ====
Line 60: Line 60:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6301, (11.84%) |7389, (6.94%) |9, (16.73%) |3, (4.09%) |3.12 |0 |0 | +| 6289, (11.82%) |7388, (6.94%) |9, (16.22%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad7616_sdz_zc706 ==== ==== ad7616_sdz_zc706 ====
Line 66: Line 66:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 5409, (2.47%) |6593, (1.51%) |9, (15.59%) |3, (1.00%) |0.78 |0 |0 | +| 5403, (2.47%) |6593, (1.51%) |9, (15.31%) |3, (1.00%) |0.78 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad7616_sdz_zed ==== ==== ad7616_sdz_zed ====
Line 72: Line 72:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6068, (11.41%) |7315, (6.88%) |9, (16.19%) |3, (4.09%) |3.12 |0 |0 | +| 6064, (11.40%) |7315, (6.88%) |9, (15.69%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad77681evb_zed ==== ==== ad77681evb_zed ====
Line 78: Line 78:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6383, (12.00%) |8047, (7.56%) |9, (17.52%) |6.5, (4.09%) |4.37 |0 |0 | +| 6381, (11.99%) |8047, (7.56%) |9, (17.01%) |6.5, (4.09%) |4.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad7768evb_zed ==== ==== ad7768evb_zed ====
Line 84: Line 84:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 9508, (17.87%) |13834, (13.00%) |9, (23.34%) |7, (4.09%) |4.54 |0 |0 | +| 10141, (19.06%) |14031, (13.19%) |9, (21.80%) |7, (4.09%) |4.54 |0 |0 |  
 +</WRAP> 
 +==== ad777x_ardz_zed ==== 
 +<WRAP round download 100%> 
 +|< 100% 15% 15% 15% 15% 15% 15%>| 
 +^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ 
 +| 7540, (14.17%) |10039, (9.44%) |9, (18.53%) |6, (4.09%) |4.19 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vck190 ==== ==== ad9081_fmca_ebz_vck190 ====
Line 90: Line 96:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 35780, (3.98%) |40219, (2.23%) |64, (8.34%) |139, (3.25%) |8.81 |0 |0 | +| 35797, (3.98%) |40245, (2.24%) |64, (8.37%) |139, (3.25%) |8.81 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118 ==== ==== ad9081_fmca_ebz_vcu118 ====
Line 96: Line 102:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 66896, (5.66%) |94448, (3.99%) |39, (18.27%) |730, (0.57%) |17.18 |0 |0 | +| 66844, (5.65%) |94395, (3.99%) |39, (18.25%) |730, (0.57%) |17.18 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118_204c-txmode10-rxmode11 ==== ==== ad9081_fmca_ebz_vcu118_204c-txmode10-rxmode11 ====
Line 102: Line 108:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 81608, (6.90%) |106333, (4.50%) |71, (16.50%) |478, (1.04%) |11.58 |0 |0 | +| 81498, (6.89%) |106338, (4.50%) |71, (16.65%) |478, (1.04%) |11.58 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118_204c-txmode10-rxmode11-24-75Gbps ==== ==== ad9081_fmca_ebz_vcu118_204c-txmode10-rxmode11-24-75Gbps ====
Line 108: Line 114:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 81635, (6.91%) |106318, (4.50%) |71, (16.50%) |478, (1.04%) |11.58 |0 |0 | +| 81550, (6.90%) |106562, (4.51%) |71, (16.65%) |478, (1.04%) |11.58 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118_204c-txmode23-rxmode25 ==== ==== ad9081_fmca_ebz_vcu118_204c-txmode23-rxmode25 ====
Line 114: Line 120:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 112246, (9.49%) |137300, (5.81%) |135, (14.27%) |485, (1.97%) |12.21 |0 |0 | +| 112262, (9.50%) |137302, (5.81%) |135, (14.14%) |485, (1.97%) |12.21 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118_204c-txmode23-rxmode25-24-75Gbps ==== ==== ad9081_fmca_ebz_vcu118_204c-txmode23-rxmode25-24-75Gbps ====
Line 120: Line 126:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 112233, (9.49%) |137281, (5.81%) |135, (14.27%) |485, (1.97%) |12.21 |0 |0 | +| 112289, (9.50%) |137295, (5.81%) |135, (14.14%) |485, (1.97%) |12.21 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118_204c-txmode24-rxmode26-24-75Gbps ==== ==== ad9081_fmca_ebz_vcu118_204c-txmode24-rxmode26-24-75Gbps ====
Line 126: Line 132:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 188536, (15.95%) |220472, (9.32%) |263, (12.23%) |769, (3.85%) |19.73 |0 |0 | +| 188394, (15.94%) |220591, (9.33%) |263, (12.11%) |769, (3.85%) |19.73 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu118_m4_l8 ==== ==== ad9081_fmca_ebz_vcu118_m4_l8 ====
Line 132: Line 138:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 83627, (7.07%) |109371, (4.63%) |71, (16.59%) |478, (1.04%) |11.58 |0 |0 | +| 83601, (7.07%) |109622, (4.64%) |71, (16.62%) |478, (1.04%) |11.58 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu128 ==== ==== ad9081_fmca_ebz_vcu128 ====
Line 138: Line 144:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 74087, (5.68%) |106850, (4.10%) |39, (18.76%) |233, (0.43%) |6.00 |0 |0 | +| 74173, (5.69%) |106822, (4.10%) |39, (18.52%) |233, (0.43%) |6.00 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_vcu128_m4_l8 ==== ==== ad9081_fmca_ebz_vcu128_m4_l8 ====
Line 144: Line 150:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 91268, (7.00%) |123972, (4.75%) |71, (16.94%) |233, (0.79%) |6.18 |0 |0 | +| 91509, (7.02%) |124337, (4.77%) |71, (16.79%) |233, (0.79%) |6.18 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_zc706 ==== ==== ad9081_fmca_ebz_zc706 ====
Line 150: Line 156:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 32348, (14.80%) |42382, (9.69%) |41, (15.39%) |266, (4.56%) |26.69 |0 |0 | +| 32297, (14.77%) |42398, (9.70%) |41, (15.31%) |266, (4.56%) |26.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_zc706_np12 ==== ==== ad9081_fmca_ebz_zc706_np12 ====
Line 156: Line 162:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 31178, (14.26%) |40649, (9.30%) |41, (14.98%) |266, (4.56%) |26.69 |0 |0 | +| 31201, (14.27%) |40679, (9.30%) |41, (14.90%) |266, (4.56%) |26.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_zcu102 ==== ==== ad9081_fmca_ebz_zcu102 ====
Line 162: Line 168:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 27420, (10.00%) |37800, (6.90%) |32, (14.42%) |531, (1.27%) |29.75 |0 |0 | +| 27427, (10.01%) |37818, (6.90%) |32, (14.38%) |531, (1.27%) |29.75 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_zcu102_204b-txmode9-rxmode4 ==== ==== ad9081_fmca_ebz_zcu102_204b-txmode9-rxmode4 ====
Line 168: Line 174:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 27107, (9.89%) |36913, (6.73%) |32, (13.75%) |531, (1.27%) |29.75 |0 |0 | +| 27109, (9.89%) |36979, (6.75%) |32, (13.74%) |531, (1.27%) |29.75 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_zcu102_204c-txmode0-rxmode1 ==== ==== ad9081_fmca_ebz_zcu102_204c-txmode0-rxmode1 ====
Line 174: Line 180:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 25679, (9.37%) |35233, (6.43%) |32, (14.02%) |531, (1.27%) |29.75 |0 |0 | +| 25671, (9.37%) |35250, (6.43%) |32, (13.87%) |531, (1.27%) |29.75 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9081_fmca_ebz_zcu102_m4_l8 ==== ==== ad9081_fmca_ebz_zcu102_m4_l8 ====
Line 180: Line 186:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 44144, (16.11%) |52750, (9.62%) |64, (12.36%) |279, (2.54%) |16.57 |0 |0 | +| 44097, (16.09%) |52745, (9.62%) |64, (12.43%) |279, (2.54%) |16.57 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9082_fmca_ebz_vcu118 ==== ==== ad9082_fmca_ebz_vcu118 ====
Line 186: Line 192:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 83613, (7.07%) |109394, (4.63%) |71, (16.58%) |478, (1.04%) |11.58 |0 |0 | +| 83555, (7.07%) |109516, (4.63%) |71, (16.61%) |478, (1.04%) |11.58 |0 |2 | 
 </WRAP> </WRAP>
 ==== ad9082_fmca_ebz_zc706 ==== ==== ad9082_fmca_ebz_zc706 ====
Line 192: Line 198:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 49231, (22.52%) |58074, (13.28%) |73, (13.22%) |146, (8.11%) |17.45 |0 |0 | +| 32319, (14.78%) |42399, (9.70%) |41, (15.30%) |266, (4.56%) |26.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9082_fmca_ebz_zcu102 ==== ==== ad9082_fmca_ebz_zcu102 ====
Line 198: Line 204:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 44151, (16.11%) |52733, (9.62%) |64, (12.37%) |279, (2.54%) |16.57 |0 |3 | +| 44092, (16.09%) |52748, (9.62%) |64, (12.42%) |279, (2.54%) |16.57 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9083_evb_zcu102 ==== ==== ad9083_evb_zcu102 ====
Line 204: Line 210:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 11394, (4.16%) |13569, (2.48%) |0, (18.46%) |28.5, (0.00%) |3.13 |0 |0 | +| 11436, (4.17%) |13697, (2.50%) |0, (18.19%) |28.5, (0.00%) |3.13 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9208_dual_ebz_vcu118 ==== ==== ad9208_dual_ebz_vcu118 ====
Line 210: Line 216:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 62784, (5.31%) |90848, (3.84%) |7, (22.38%) |320.5, (0.10%) |7.47 |0 |0 | +| 62818, (5.31%) |90832, (3.84%) |7, (22.24%) |320.5, (0.10%) |7.47 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9265_fmc_zc706 ==== ==== ad9265_fmc_zc706 ====
Line 216: Line 222:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 5455, (2.50%) |7197, (1.65%) |10, (15.81%) |3, (1.11%) |0.83 |0 |0 | +| 5457, (2.50%) |7198, (1.65%) |10, (15.58%) |3, (1.11%) |0.83 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9434_fmc_zc706 ==== ==== ad9434_fmc_zc706 ====
Line 222: Line 228:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 5435, (2.49%) |6880, (1.57%) |9, (15.38%) |3, (1.00%) |0.78 |0 |0 | +| 5426, (2.48%) |6881, (1.57%) |9, (15.10%) |3, (1.00%) |0.78 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9467_fmc_kc705 ==== ==== ad9467_fmc_kc705 ====
Line 228: Line 234:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 27391, (13.44%) |30531, (7.49%) |4, (18.14%) |48, (0.48%) |5.63 |0 |1 | +| 27390, (13.44%) |30532, (7.49%) |4, (18.12%) |48, (0.48%) |5.63 |0 |1 | 
 </WRAP> </WRAP>
 ==== ad9467_fmc_zed ==== ==== ad9467_fmc_zed ====
Line 234: Line 240:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6089, (11.45%) |7639, (7.18%) |9, (16.21%) |3, (4.09%) |3.12 |0 |0 | +| 6078, (11.42%) |7639, (7.18%) |9, (15.69%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9656_fmc_zcu102 ==== ==== ad9656_fmc_zcu102 ====
Line 240: Line 246:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 8070, (2.94%) |10170, (1.86%) |0, (21.89%) |2, (0.00%) |0.22 |0 |0 | +| 8123, (2.96%) |10171, (1.86%) |0, (21.50%) |2, (0.00%) |0.22 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9695_fmc_zcu102 ==== ==== ad9695_fmc_zcu102 ====
Line 246: Line 252:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 8067, (2.94%) |10388, (1.90%) |0, (22.71%) |14.5, (0.00%) |1.59 |0 |0 | +| 8082, (2.95%) |10385, (1.89%) |0, (22.34%) |14.5, (0.00%) |1.59 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9739a_fmc_zc706 ==== ==== ad9739a_fmc_zc706 ====
Line 252: Line 258:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 13040, (5.97%) |18992, (4.34%) |169, (16.41%) |6, (18.78%) |9.94 |0 |0 | +| 13039, (5.96%) |18992, (4.34%) |169, (16.27%) |6, (18.78%) |9.94 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad9783_ebz_zcu102 ==== ==== ad9783_ebz_zcu102 ====
Line 258: Line 264:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6564, (2.39%) |9845, (1.80%) |80, (16.80%) |2, (3.17%) |1.70 |0 |0 | +| 6559, (2.39%) |9844, (1.80%) |80, (16.83%) |2, (3.17%) |1.70 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad_fmclidar1_ebz_zc706 ==== ==== ad_fmclidar1_ebz_zc706 ====
Line 264: Line 270:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 13551, (6.20%) |16046, (3.67%) |9, (20.42%) |6, (1.00%) |1.05 |0 |91 | +| 13575, (6.21%) |16048, (3.67%) |9, (20.15%) |6, (1.00%) |1.05 |0 |87 | 
 </WRAP> </WRAP>
 ==== ad_fmclidar1_ebz_zcu102 ==== ==== ad_fmclidar1_ebz_zcu102 ====
Line 270: Line 276:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 10572, (3.86%) |13203, (2.41%) |0, (19.92%) |4, (0.00%) |0.44 |0 |0 | +| 10622, (3.88%) |13205, (2.41%) |0, (19.62%) |4, (0.00%) |0.44 |0 |0 | 
 </WRAP> </WRAP>
 ==== ad_quadmxfe1_ebz_vcu118 ==== ==== ad_quadmxfe1_ebz_vcu118 ====
Line 276: Line 282:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 179493, (15.18%) |247941, (10.49%) |263, (11.88%) |1203.5, (3.85%) |29.79 |0 |0 | +| 178800, (15.12%) |247048, (10.45%) |263, (12.60%) |1203.5, (3.85%) |29.79 |0 |0 | 
 </WRAP> </WRAP>
 ==== adaq7980_sdz_zed ==== ==== adaq7980_sdz_zed ====
Line 282: Line 288:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6201, (11.66%) |7720, (7.26%) |9, (17.17%) |3, (4.09%) |3.12 |0 |0 | +| 6188, (11.63%) |7719, (7.25%) |9, (16.68%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== adaq8092_fmc_zed ==== ==== adaq8092_fmc_zed ====
Line 288: Line 294:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6461, (12.14%) |8516, (8.00%) |11, (16.66%) |3, (5.00%) |3.57 |0 |0 | +| 6456, (12.14%) |8516, (8.00%) |11, (16.17%) |3, (5.00%) |3.57 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9001_zc706 ==== ==== adrv9001_zc706 ====
Line 294: Line 300:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 27370, (12.52%) |36621, (8.38%) |21, (12.19%) |6, (2.33%) |1.72 |0 |0 | +| 27375, (12.52%) |36623, (8.38%) |21, (12.12%) |6, (2.33%) |1.72 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9001_zcu102 ==== ==== adrv9001_zcu102 ====
Line 300: Line 306:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 25029, (9.13%) |34388, (6.27%) |12, (12.48%) |4, (0.48%) |0.46 |0 |0 | +| 25020, (9.13%) |34389, (6.27%) |12, (12.49%) |4, (0.48%) |0.46 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9001_zcu102_lvds ==== ==== adrv9001_zcu102_lvds ====
Line 306: Line 312:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 24652, (8.99%) |33974, (6.20%) |12, (12.22%) |4, (0.48%) |0.46 |0 |0 | +| 24647, (8.99%) |33978, (6.20%) |12, (12.23%) |4, (0.48%) |0.46 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9001_zed ==== ==== adrv9001_zed ====
Line 312: Line 318:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 28006, (52.64%) |37309, (35.06%) |21, (12.36%) |6, (9.55%) |6.92 |0 |0 | +| 28005, (52.64%) |37309, (35.06%) |21, (12.23%) |6, (9.55%) |6.92 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9009_zc706 ==== ==== adrv9009_zc706 ====
Line 318: Line 324:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 52254, (23.90%) |68758, (15.73%) |157, (15.94%) |40.5, (17.44%) |12.44 |0 |1 | +| 52196, (23.88%) |68753, (15.73%) |157, (15.90%) |40.5, (17.44%) |12.44 |0 |1 | 
 </WRAP> </WRAP>
 ==== adrv9009_zcu102 ==== ==== adrv9009_zcu102 ====
Line 324: Line 330:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 34238, (12.49%) |50178, (9.15%) |144, (20.01%) |520, (5.71%) |31.37 |0 |0 | +| 34226, (12.49%) |50187, (9.16%) |144, (19.89%) |520, (5.71%) |31.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9009zu11eg_adrv2crr_fmc ==== ==== adrv9009zu11eg_adrv2crr_fmc ====
Line 330: Line 336:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 61817, (20.71%) |79813, (13.37%) |35, (15.98%) |97, (1.20%) |8.69 |0 |0 | +| 61822, (20.71%) |79818, (13.37%) |35, (15.90%) |97, (1.20%) |8.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9009zu11eg_adrv2crr_fmcomms8 ==== ==== adrv9009zu11eg_adrv2crr_fmcomms8 ====
Line 336: Line 342:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 96780, (32.42%) |121469, (20.34%) |67, (12.97%) |165.5, (2.29%) |14.93 |0 |0 | +| 96660, (32.38%) |121460, (20.34%) |67, (13.04%) |165.5, (2.29%) |14.93 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9009zu11eg_adrv2crr_fmcxmwbr1 ==== ==== adrv9009zu11eg_adrv2crr_fmcxmwbr1 ====
Line 342: Line 348:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 63959, (21.42%) |82745, (13.86%) |35, (15.69%) |97, (1.20%) |8.69 |0 |0 | +| 63957, (21.42%) |82724, (13.85%) |35, (15.62%) |97, (1.20%) |8.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9009zu11eg_adrv2crr_xmicrowave ==== ==== adrv9009zu11eg_adrv2crr_xmicrowave ====
Line 348: Line 354:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 63976, (21.43%) |82732, (13.86%) |35, (15.68%) |97, (1.20%) |8.69 |0 |0 | +| 63957, (21.42%) |82719, (13.85%) |35, (15.62%) |97, (1.20%) |8.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9361z7035_ccbob_cmos ==== ==== adrv9361z7035_ccbob_cmos ====
Line 354: Line 360:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 13313, (7.74%) |20968, (6.10%) |28, (15.35%) |4, (3.11%) |1.96 |0 |0 | +| 13300, (7.74%) |20969, (6.10%) |28, (15.20%) |4, (3.11%) |1.96 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9361z7035_ccbob_lvds ==== ==== adrv9361z7035_ccbob_lvds ====
Line 360: Line 366:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 13210, (7.68%) |20922, (6.09%) |28, (15.42%) |4, (3.11%) |1.96 |0 |0 | +| 13213, (7.69%) |20923, (6.09%) |28, (15.26%) |4, (3.11%) |1.96 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9361z7035_ccfmc_lvds ==== ==== adrv9361z7035_ccfmc_lvds ====
Line 366: Line 372:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 15921, (9.26%) |24515, (7.13%) |37, (14.55%) |6, (4.11%) |2.66 |0 |5 | +| 15939, (9.27%) |24516, (7.13%) |37, (14.41%) |6, (4.11%) |2.66 |0 |5 | 
 </WRAP> </WRAP>
 ==== adrv9361z7035_ccpackrf_lvds ==== ==== adrv9361z7035_ccpackrf_lvds ====
Line 372: Line 378:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 12626, (7.34%) |19599, (5.70%) |28, (14.27%) |4, (3.11%) |1.96 |0 |0 | +| 12636, (7.35%) |19598, (5.70%) |28, (14.08%) |4, (3.11%) |1.96 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9364z7020_ccbob_cmos ==== ==== adrv9364z7020_ccbob_cmos ====
Line 378: Line 384:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 9288, (17.46%) |14141, (13.29%) |14, (14.67%) |4, (6.36%) |4.61 |0 |0 | +| 9287, (17.46%) |14142, (13.29%) |14, (14.49%) |4, (6.36%) |4.61 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9364z7020_ccbob_lvds ==== ==== adrv9364z7020_ccbob_lvds ====
Line 384: Line 390:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 9211, (17.31%) |14110, (13.26%) |14, (14.73%) |4, (6.36%) |4.61 |0 |0 | +| 9205, (17.30%) |14106, (13.26%) |14, (14.46%) |4, (6.36%) |4.61 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9364z7020_ccpackrf_lvds ==== ==== adrv9364z7020_ccpackrf_lvds ====
Line 390: Line 396:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 9293, (17.47%) |14078, (13.23%) |14, (15.03%) |4, (6.36%) |4.61 |0 |0 | +| 9300, (17.48%) |14078, (13.23%) |14, (14.79%) |4, (6.36%) |4.61 |0 |0 | 
 </WRAP> </WRAP>
 ==== adrv9371x_kcu105 ==== ==== adrv9371x_kcu105 ====
Line 396: Line 402:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 73289, (30.49%) |103737, (21.40%) |151, (19.19%) |338, (7.86%) |32.09 |0 |0 | +| 73306, (30.50%) |103738, (21.40%) |151, (19.12%) |338, (7.86%) |32.09 |2 |5 | 
 </WRAP> </WRAP>
 ==== adrv9371x_zc706 ==== ==== adrv9371x_zc706 ====
Line 402: Line 408:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 52662, (24.09%) |69243, (15.84%) |157, (16.76%) |40.5, (17.44%) |12.44 |0 |1 | +| 52623, (24.07%) |69238, (15.84%) |157, (16.72%) |40.5, (17.44%) |12.44 |0 |1 | 
 </WRAP> </WRAP>
 ==== adrv9371x_zcu102 ==== ==== adrv9371x_zcu102 ====
Line 408: Line 414:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 34561, (12.61%) |50807, (9.27%) |144, (21.64%) |518, (5.71%) |31.25 |0 |0 | +| 34542, (12.60%) |50807, (9.27%) |144, (21.54%) |518, (5.71%) |31.25 |0 |0 | 
 </WRAP> </WRAP>
 ==== adv7511_zc702 ==== ==== adv7511_zc702 ====
Line 414: Line 420:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3456, (6.50%) |4600, (4.32%) |9, (16.54%) |2, (4.09%) |2.76 |0 |0 | +| 3462, (6.51%) |4599, (4.32%) |9, (16.57%) |2, (4.09%) |2.76 |0 |0 | 
 </WRAP> </WRAP>
 ==== adv7511_zc706 ==== ==== adv7511_zc706 ====
Line 420: Line 426:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3431, (1.57%) |4462, (1.02%) |9, (16.03%) |2, (1.00%) |0.69 |0 |0 | +| 3422, (1.57%) |4461, (1.02%) |9, (15.51%) |2, (1.00%) |0.69 |0 |0 | 
 </WRAP> </WRAP>
 ==== adv7511_zed ==== ==== adv7511_zed ====
Line 426: Line 432:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 4121, (7.75%) |5195, (4.88%) |9, (17.15%) |2, (4.09%) |2.76 |0 |0 | +| 4104, (7.71%) |5193, (4.88%) |9, (16.37%) |2, (4.09%) |2.76 |0 |0 | 
 </WRAP> </WRAP>
 ==== cn0363_zed ==== ==== cn0363_zed ====
Line 432: Line 438:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 7685, (14.45%) |10264, (9.65%) |13, (15.50%) |9.5, (5.91%) |6.35 |0 |0 |  +| 7683, (14.44%) |10266, (9.65%) |13, (15.05%) |9.5, (5.91%) |6.35 |0 |0 | 
-</WRAP> +
-==== cn0501_coraz7s ==== +
-<WRAP round download 100%> +
-|< 100% 15% 15% 15% 15% 15% 15%>| +
-^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ +
-| 5915, (41.08%) |8636, (29.99%) |0, (20.72%) |5, (0.00%) |10.00 |0 |0 | +
 </WRAP> </WRAP>
-==== cn0506_mii_zc706 ====+==== cn0506_zc706 ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3457, (1.58%) |4491, (1.03%) |9, (15.86%) |2, (1.00%) |0.69 |0 |0 | +| 3718, (1.70%) |4990, (1.14%) |9, (16.25%) |2, (1.00%) |0.69 |0 |20 | 
 </WRAP> </WRAP>
-==== cn0506_mii_zcu102 ====+==== cn0506_zc706_mii ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 629, (0.23%) |777, (0.14%) |0, (11.10%) |0, (0.00%) |0.00 |0 |0 | +| 3433, (1.57%) |4492, (1.03%) |9, (15.58%) |2, (1.00%) |0.69 |0 |0 | 
 </WRAP> </WRAP>
-==== cn0506_mii_zed ====+==== cn0506_zc706_rmii ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 4123, (7.75%) |5223, (4.91%) |9, (17.09%) |2, (4.09%) |2.76 |0 |0 | +| 3520, (1.61%) |4716, (1.08%) |9, (16.12%) |2, (1.00%) |0.69 |0 |0 | 
 </WRAP> </WRAP>
-==== cn0506_rgmii_zc706 ====+==== cn0506_zcu102 ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3739, (1.71%) |4990, (1.14%) |9, (16.58%) |2, (1.00%) |0.69 |0 |20 | +| 897, (0.33%) |1258, (0.23%) |0, (15.29%) |0, (0.00%) |0.00 |0 |0 | 
 </WRAP> </WRAP>
-==== cn0506_rgmii_zcu102 ====+==== cn0506_zcu102_mii ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 923, (0.34%) |1258, (0.23%) |0, (14.76%) |0, (0.00%) |0.00 |0 |0 | +| 628, (0.23%) |778, (0.14%) |0, (11.33%) |0, (0.00%) |0.00 |0 |0 | 
 </WRAP> </WRAP>
-==== cn0506_rgmii_zed ====+==== cn0506_zcu102_rmii ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 4412, (8.29%) |5722, (5.38%) |9, (17.61%) |2, (4.09%) |2.76 |0 |20 | +| 703, (0.26%) |999, (0.18%) |0, (14.37%) |0, (0.00%) |0.00 |0 |0 | 
 </WRAP> </WRAP>
-==== cn0506_rmii_zc706 ====+==== cn0506_zed ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3543, (1.62%) |4715, (1.08%) |9, (16.54%) |2, (1.00%) |0.69 |0 |0 | +| 4399, (8.27%) |5722, (5.38%) |9, (16.93%) |2, (4.09%) |2.76 |0 |20 | 
 </WRAP> </WRAP>
-==== cn0506_rmii_zcu102 ====+==== cn0506_zed_mii ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 706, (0.26%) |999, (0.18%) |0, (14.40%) |0, (0.00%) |0.00 |0 |0 | +| 4117, (7.74%) |5224, (4.91%) |9, (16.36%) |2, (4.09%) |2.76 |0 |0 | 
 </WRAP> </WRAP>
-==== cn0506_rmii_zed ====+==== cn0506_zed_rmii ====
 <WRAP round download 100%> <WRAP round download 100%>
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 4207, (7.91%) |5447, (5.12%) |9, (17.60%) |2, (4.09%) |2.76 |0 |0 | +| 4203, (7.90%) |5448, (5.12%) |9, (16.87%) |2, (4.09%) |2.76 |0 |0 | 
 </WRAP> </WRAP>
 ==== cn0540_coraz7s ==== ==== cn0540_coraz7s ====
Line 498: Line 498:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3524, (24.47%) |4411, (15.32%) |0, (20.61%) |4.5, (0.00%) |9.00 |0 |0 | +| 3517, (24.42%) |4410, (15.31%) |0, (20.11%) |4.5, (0.00%) |9.00 |0 |0 | 
 </WRAP> </WRAP>
 ==== cn0561_coraz7s ==== ==== cn0561_coraz7s ====
Line 504: Line 504:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3124, (21.69%) |4430, (15.38%) |0, (20.14%) |4.5, (0.00%) |9.00 |0 |0 | +| 3123, (21.69%) |4430, (15.38%) |0, (20.14%) |4.5, (0.00%) |9.00 |0 |0 | 
 </WRAP> </WRAP>
 ==== cn0561_zed ==== ==== cn0561_zed ====
Line 510: Line 510:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 7597, (14.28%) |10768, (10.12%) |9, (22.03%) |6.5, (4.09%) |4.37 |0 |0 | +| 7586, (14.26%) |10767, (10.12%) |9, (21.63%) |6.5, (4.09%) |4.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== cn0577_zed ==== ==== cn0577_zed ====
Line 516: Line 516:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6458, (12.14%) |8737, (8.21%) |9, (16.70%) |3, (4.09%) |3.12 |0 |0 | +| 6432, (12.09%) |8738, (8.21%) |9, (16.17%) |3, (4.09%) |3.12 |0 |0 | 
 </WRAP> </WRAP>
 ==== dac_fmc_ebz_vcu118 ==== ==== dac_fmc_ebz_vcu118 ====
Line 522: Line 522:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 54398, (4.60%) |72781, (3.08%) |23, (16.99%) |267, (0.34%) |6.35 |0 |0 | +| 54406, (4.60%) |72762, (3.08%) |23, (16.98%) |267, (0.34%) |6.35 |0 |0 | 
 </WRAP> </WRAP>
 ==== dac_fmc_ebz_zc706 ==== ==== dac_fmc_ebz_zc706 ====
Line 528: Line 528:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 20073, (9.18%) |24169, (5.53%) |25, (8.75%) |70, (2.78%) |7.81 |0 |0 | +| 20057, (9.18%) |24169, (5.53%) |25, (8.63%) |70, (2.78%) |7.81 |0 |0 | 
 </WRAP> </WRAP>
 ==== dac_fmc_ebz_zcu102 ==== ==== dac_fmc_ebz_zcu102 ====
Line 534: Line 534:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 17169, (6.26%) |20725, (3.78%) |16, (8.77%) |36, (0.63%) |2.29 |0 |0 | +| 17151, (6.26%) |20728, (3.78%) |16, (8.72%) |36, (0.63%) |2.29 |0 |0 | 
 </WRAP> </WRAP>
 ==== daq2_kc705 ==== ==== daq2_kc705 ====
Line 540: Line 540:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 51379, (25.21%) |59221, (14.53%) |20, (13.84%) |311, (2.38%) |36.13 |0 |1 | +| 51384, (25.21%) |59242, (14.53%) |20, (13.80%) |311, (2.38%) |36.13 |0 |1 | 
 </WRAP> </WRAP>
 ==== daq2_kcu105 ==== ==== daq2_kcu105 ====
Line 546: Line 546:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 63211, (26.08%) |84545, (17.44%) |23, (17.40%) |468, (1.20%) |39.60 |0 |0 | +| 63240, (26.09%) |84567, (17.44%) |23, (17.34%) |468, (1.20%) |39.60 |6 |6 | 
 </WRAP> </WRAP>
 ==== daq2_zc706 ==== ==== daq2_zc706 ====
Line 552: Line 552:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 40444, (18.50%) |44459, (10.17%) |25, (11.38%) |282, (2.78%) |27.26 |0 |1 | +| 40420, (18.49%) |44490, (10.18%) |25, (11.33%) |282, (2.78%) |27.26 |0 |1 | 
 </WRAP> </WRAP>
 ==== daq2_zcu102 ==== ==== daq2_zcu102 ====
Line 558: Line 558:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 24555, (8.96%) |30399, (5.55%) |16, (11.93%) |520, (0.63%) |28.83 |0 |0 | +| 24573, (8.97%) |30424, (5.55%) |16, (11.83%) |520, (0.63%) |28.83 |0 |0 | 
 </WRAP> </WRAP>
 ==== daq3_kcu105 ==== ==== daq3_kcu105 ====
Line 564: Line 564:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 63403, (26.16%) |86025, (17.74%) |23, (17.65%) |438, (1.20%) |37.10 |4 |7 | +| 63444, (26.17%) |86085, (17.76%) |23, (17.58%) |438, (1.20%) |37.10 |3 |9 | 
 </WRAP> </WRAP>
 ==== daq3_vcu118 ==== ==== daq3_vcu118 ====
Line 570: Line 570:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 64076, (5.42%) |87302, (3.69%) |23, (18.03%) |561, (0.34%) |13.15 |0 |0 | +| 64046, (5.42%) |87272, (3.69%) |23, (17.99%) |561, (0.34%) |13.15 |0 |0 | 
 </WRAP> </WRAP>
 ==== daq3_zc706 ==== ==== daq3_zc706 ====
Line 576: Line 576:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 42979, (19.66%) |52220, (11.94%) |25, (12.29%) |279.5, (2.78%) |27.03 |0 |0 | +| 42954, (19.65%) |52220, (11.94%) |25, (12.22%) |279.5, (2.78%) |27.03 |0 |0 | 
 </WRAP> </WRAP>
 ==== daq3_zcu102 ==== ==== daq3_zcu102 ====
Line 582: Line 582:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 24086, (8.79%) |29559, (5.39%) |16, (13.11%) |262, (0.63%) |14.68 |0 |0 | +| 24086, (8.79%) |29559, (5.39%) |16, (12.97%) |262, (0.63%) |14.68 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcadc2_vc707 ==== ==== fmcadc2_vc707 ====
Line 588: Line 588:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 46867, (15.44%) |55455, (9.13%) |4, (14.91%) |660, (0.14%) |32.11 |0 |1 | +| 46882, (15.44%) |55469, (9.14%) |4, (14.83%) |660, (0.14%) |32.11 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcadc2_zc706 ==== ==== fmcadc2_zc706 ====
Line 594: Line 594:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 28610, (13.09%) |34712, (7.94%) |9, (14.87%) |18.5, (1.00%) |2.20 |0 |1 | +| 28566, (13.07%) |34710, (7.94%) |9, (14.76%) |18.5, (1.00%) |2.20 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcadc5_vc707 ==== ==== fmcadc5_vc707 ====
Line 600: Line 600:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 62463, (20.57%) |73543, (12.11%) |36, (16.67%) |674, (1.29%) |33.37 |0 |1 | +| 62466, (20.58%) |73555, (12.11%) |36, (16.55%) |674, (1.29%) |33.37 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcjesdadc1_kc705 ==== ==== fmcjesdadc1_kc705 ====
Line 606: Line 606:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 35243, (17.29%) |40087, (9.83%) |4, (18.10%) |55, (0.48%) |6.42 |0 |1 | +| 35243, (17.29%) |40096, (9.84%) |4, (18.01%) |55, (0.48%) |6.42 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcjesdadc1_vc707 ==== ==== fmcjesdadc1_vc707 ====
Line 612: Line 612:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 44638, (14.70%) |52103, (8.58%) |4, (15.45%) |151, (0.14%) |7.40 |0 |1 | +| 44623, (14.70%) |52094, (8.58%) |4, (15.39%) |151, (0.14%) |7.40 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcjesdadc1_zc706 ==== ==== fmcjesdadc1_zc706 ====
Line 618: Line 618:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 11358, (5.20%) |13675, (3.13%) |9, (20.50%) |4, (1.00%) |0.86 |0 |0 | +| 11344, (5.19%) |13675, (3.13%) |9, (20.22%) |4, (1.00%) |0.86 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms11_zc706 ==== ==== fmcomms11_zc706 ====
Line 624: Line 624:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 58748, (26.87%) |68249, (15.61%) |41, (9.52%) |282.5, (4.56%) |28.20 |0 |0 | +| 58736, (26.87%) |68244, (15.61%) |41, (9.44%) |282.5, (4.56%) |28.20 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms2_kc705 ==== ==== fmcomms2_kc705 ====
Line 630: Line 630:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 36959, (18.13%) |46600, (11.43%) |32, (16.67%) |51, (3.81%) |7.64 |0 |1 | +| 36941, (18.13%) |46584, (11.43%) |32, (16.65%) |51, (3.81%) |7.64 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcomms2_kcu105 ==== ==== fmcomms2_kcu105 ====
Line 636: Line 636:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 49502, (20.59%) |71085, (14.66%) |35, (18.35%) |80, (1.82%) |7.58 |0 |0 | +| 49492, (20.59%) |71084, (14.66%) |35, (18.34%) |80, (1.82%) |7.58 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms2_vc707 ==== ==== fmcomms2_vc707 ====
Line 642: Line 642:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 47693, (15.71%) |60138, (9.90%) |32, (13.51%) |151, (1.14%) |7.90 |0 |1 | +| 47681, (15.71%) |60157, (9.91%) |32, (13.50%) |151, (1.14%) |7.90 |0 |1 | 
 </WRAP> </WRAP>
 ==== fmcomms2_zc702 ==== ==== fmcomms2_zc702 ====
Line 648: Line 648:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 14619, (27.48%) |22470, (21.12%) |37, (14.37%) |6, (16.82%) |10.55 |0 |0 | +| 14624, (27.49%) |22472, (21.12%) |37, (14.36%) |6, (16.82%) |10.55 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms2_zc706 ==== ==== fmcomms2_zc706 ====
Line 654: Line 654:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 14572, (6.67%) |22329, (5.11%) |37, (14.23%) |6, (4.11%) |2.61 |0 |0 | +| 14567, (6.66%) |22331, (5.11%) |37, (14.09%) |6, (4.11%) |2.61 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms2_zcu102 ==== ==== fmcomms2_zcu102 ====
Line 660: Line 660:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 11544, (4.21%) |18964, (3.46%) |28, (12.05%) |4, (1.11%) |0.78 |0 |0 | +| 11550, (4.21%) |18967, (3.46%) |28, (12.09%) |4, (1.11%) |0.78 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms2_zed ==== ==== fmcomms2_zed ====
Line 666: Line 666:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 14375, (27.02%) |20413, (19.19%) |37, (14.74%) |6, (16.82%) |10.55 |0 |0 | +| 14365, (27.00%) |20413, (19.19%) |37, (14.54%) |6, (16.82%) |10.55 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms5_zc702 ==== ==== fmcomms5_zc702 ====
Line 672: Line 672:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 23142, (43.50%) |37801, (35.53%) |65, (13.92%) |10, (29.55%) |18.34 |0 |0 | +| 23151, (43.52%) |37801, (35.53%) |65, (13.92%) |10, (29.55%) |18.34 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms5_zc706 ==== ==== fmcomms5_zc706 ====
Line 678: Line 678:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 23092, (10.56%) |37474, (8.57%) |65, (13.41%) |10, (7.22%) |4.53 |0 |0 | +| 23081, (10.56%) |37477, (8.57%) |65, (13.32%) |10, (7.22%) |4.53 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms5_zcu102 ==== ==== fmcomms5_zcu102 ====
Line 684: Line 684:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 20097, (7.33%) |34226, (6.24%) |56, (11.54%) |8, (2.22%) |1.55 |0 |0 | +| 20047, (7.31%) |34230, (6.24%) |56, (11.60%) |8, (2.22%) |1.55 |0 |0 | 
 </WRAP> </WRAP>
 ==== fmcomms8_zcu102 ==== ==== fmcomms8_zcu102 ====
Line 690: Line 690:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 45155, (16.48%) |56645, (10.33%) |32, (12.33%) |524, (1.27%) |29.37 |0 |0 | +| 45143, (16.47%) |56644, (10.33%) |32, (12.23%) |524, (1.27%) |29.37 |0 |0 | 
 </WRAP> </WRAP>
 ==== imageon_zed ==== ==== imageon_zed ====
Line 696: Line 696:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 6840, (12.86%) |8565, (8.05%) |17, (16.05%) |3, (7.73%) |4.94 |0 |0 | +| 6832, (12.84%) |8565, (8.05%) |17, (15.37%) |3, (7.73%) |4.94 |0 |0 | 
 </WRAP> </WRAP>
 ==== m2k_standalone ==== ==== m2k_standalone ====
Line 702: Line 702:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 10037, (57.03%) |15234, (43.28%) |30, (11.19%) |17, (37.50%) |32.91 |0 |0 | +| 10020, (56.93%) |15235, (43.28%) |30, (11.17%) |17, (37.50%) |32.91 |0 |0 | 
 </WRAP> </WRAP>
 ==== pluto ==== ==== pluto ====
Line 708: Line 708:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 11908, (67.66%) |20782, (59.04%) |72, (18.54%) |2, (90.00%) |46.66 |0 |0 | +| 11911, (67.68%) |20782, (59.04%) |72, (18.41%) |2, (90.00%) |46.66 |0 |0 | 
 </WRAP> </WRAP>
 ==== pluto_ng ==== ==== pluto_ng ====
Line 714: Line 714:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 24934, (35.34%) |34487, (24.44%) |12, (12.28%) |4, (3.33%) |2.59 |0 |0 | +| 24936, (35.34%) |34490, (24.44%) |12, (12.32%) |4, (3.33%) |2.59 |0 |0 | 
 </WRAP> </WRAP>
 ==== pulsar_adc_pmdz_coraz7s ==== ==== pulsar_adc_pmdz_coraz7s ====
Line 720: Line 720:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 3334, (23.15%) |4739, (16.45%) |0, (21.22%) |4.5, (0.00%) |9.00 |0 |0 | +| 3337, (23.17%) |4739, (16.45%) |0, (21.25%) |4.5, (0.00%) |9.00 |0 |0 | 
 </WRAP> </WRAP>
 ==== sidekiqz2 ==== ==== sidekiqz2 ====
Line 726: Line 726:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 11913, (67.69%) |20782, (59.04%) |72, (18.55%) |2, (90.00%) |46.66 |0 |0 | +| 11910, (67.67%) |20782, (59.04%) |72, (18.41%) |2, (90.00%) |46.66 |0 |0 | 
 </WRAP> </WRAP>
 ==== usrpe31x ==== ==== usrpe31x ====
Line 732: Line 732:
 |< 100% 15% 15% 15% 15% 15% 15%>| |< 100% 15% 15% 15% 15% 15% 15%>|
 ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^ ^LUT ^FD ^DSP48 ^RAMB/FIFO ^BUFG ^MMCM ^PLL ^
-| 11838, (22.25%) |18820, (17.69%) |28, (14.34%) |2, (12.73%) |7.08 |0 |0 | +| 11840, (22.26%) |18820, (17.69%) |28, (14.35%) |2, (12.73%) |7.08 |0 |0 | 
 </WRAP> </WRAP>
  
resources/fpga/docs/hdl/utilization_master.txt · Last modified: 10 Jan 2024 13:07 by Stanca-Florina Pop

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