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Files in resources:fpga:docs:axi_tdd
- axi_tdd_diagram.png
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- 07 Oct 2022 06:47
- 115 KB
- axi_tdd_fsm.png
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- 07 Oct 2022 06:37
- 132.1 KB
- axi_tdd_vivado.png
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- 07 Oct 2022 06:36
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- Date:
- 19 May 2017 17:12
- Filename:
- boot.zip
- Size:
- 925KB
- References for:
- Integrate FIR filters into the FMCOMMS2 HDL design
resources/fpga/docs/hdl/regmap.txt · Last modified: 19 Feb 2024 13:35 by Adrian Costina