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resources:fpga:docs:hdl:regmap [30 Sep 2022 12:56]
Alin-Tudor Sferle base: Update description for RD_RAW_DATA field.
resources:fpga:docs:hdl:regmap [30 Sep 2022 13:22] (current)
Alin-Tudor Sferle V2 - base: Update description for RD_RAW_DATA field.
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 |::: |::: |[9] |SCALECORRECTION_ONLY |RO |0x0 |If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) | |::: |::: |[9] |SCALECORRECTION_ONLY |RO |0x0 |If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) |
 |::: |::: |[12] |EXT_SYNC |RO |0x0 |If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. | |::: |::: |[12] |EXT_SYNC |RO |0x0 |If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. |
-|::: |::: |[13] |RD_RAW_DATA |RO |0x0 |If set, the ADC has the capability to read raw data in the specific ​register from adc_channel. |+|::: |::: |[13] |RD_RAW_DATA |RO |0x0 |If set, the ADC has the capability to read raw data in register ​REG_CHAN_RAW_DATA ​from adc_channel. |
 ^0x0004 ^0x0010 ^REG_PPS_IRQ_MASK ^^^^PPS Interrupt mask ^ ^0x0004 ^0x0010 ^REG_PPS_IRQ_MASK ^^^^PPS Interrupt mask ^
 | | |[0] |PPS_IRQ_MASK |RW |0x1 |Mask bit for the 1PPS receiver interrupt | | | |[0] |PPS_IRQ_MASK |RW |0x1 |Mask bit for the 1PPS receiver interrupt |
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 |::: |::: |[0] |OVER_RANGE |RW1C |0x0 |If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. | |::: |::: |[0] |OVER_RANGE |RW1C |0x0 |If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. |
 ^0x0102 ^0x0408 ^REG_CHAN_RAW_DATA ^^^^ADC Raw Data Reading ^ ^0x0102 ^0x0408 ^REG_CHAN_RAW_DATA ^^^^ADC Raw Data Reading ^
-| | |[31:0] |ADC_READ_DATA[30:0] |RO |0x0000 |Raw data read from the ADC. |+| | |[31:0] |ADC_READ_DATA[31:0] |RO |0x0000 |Raw data read from the ADC. |
 ^0x0104 ^0x0410 ^REG_CHAN_CNTRL_1 ^^^^ADC Interface Control & Status ^ ^0x0104 ^0x0410 ^REG_CHAN_CNTRL_1 ^^^^ADC Interface Control & Status ^
 | | |[31:16] |DCFILT_OFFSET[15:​0] |RW |0x0000 |DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). | | | |[31:16] |DCFILT_OFFSET[15:​0] |RW |0x0000 |DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
resources/fpga/docs/hdl/regmap.txt · Last modified: 30 Sep 2022 13:22 by Alin-Tudor Sferle