In general, a given reference design for an FMC board is deployed to just a few carriers, although several FPGA boards are supported in ADI's HDL repository. The simple reason behind this practice is that it would create a tremendous maintenance workload, that would require a lot of human resources, and would increase the required time for testing. The general rule of thumb is to support a given project with a fairly popular carrier (e.g. ZC706 or A10SoC), which is powerful enough to showcase the board features and maximum performance.
All the HDL projects were designed to maximize source code reuse, minimize maintainability and simplify portability. The result of these design goals is that porting a given project to another carrier is fairly simple if the user respects a couple of guidelines.
The main scope of this wiki page is to discuss these guidelines and provide simple indications for users who wants to port a project to a non-supported carrier.
There are two types of FMC connectors: LPC (Low Pin Count) and HPC (High Pin Count). In general, an FMC board is using the FMC connector type that has enough pins for the required interfaces between the I/O devices and FPGA. A carrier with an FMC HPC connector can host FMC boards with an LPC or HPC connector, but a carrier with an FMC LPC can host a board just with an FMC LPC connector.
The most important things to check before porting are related to the ANSI/VITA 57.1 standard (the list is not necessarily exhaustive):
At HDL Architecture wiki it is described a generic base design and possible components of it. The user should look at it as a suggestion only.
In this section, we are presenting all the necessary steps to create a base design for the Xilinx ZCU102 development board.
First, you need to create a new directory in ~/projects/common with the name of the carrier.
[~/hdl]cd projects/common [~/hdl]mkdir zcu102
The zcu102 directory must contain the following files:
You should define the board and its device in the project flow script, called (adi_project_xilinx.tcl), by adding the following lines to the beginning of the adi_project_create process:
if [regexp "_zcu102$" $project_name] { set p_device "xczu9eg-ffvb1156-1-i-es1" set p_board "xilinx.com:zcu102:part0:1.2" set sys_zynq 2 }
The sys_zynq constant variable should be set in the following way:
To create a new base design for a given Intel FPGA carrier board, the following steps should be taken (the A10SoC carrier was used as an example).
The following files should be created or copied into the directory:
You should define the board and its device in the flow script (adi_project_intel.tcl), by adding the following lines to the beginning of the adi_project_altera process:
if [regexp "_a10soc$" $project_name] { set family "Arria 10" set device 10AS066N3F40E2SG set system_qip_file system_bd/system_bd.qip }
To follow the project framework as much as possible, the easiest way is to copy all the projects files from an already existing project and modifying those files to support the new carrier. A project for a Xilinx FPGA board should contain the following files:
To follow the project framework as much as possible the easiest way is to copy all the projects file from an already existing project and modifying those files to support the new carrier. A project for an Intel FPGA board should contain the following files:
The easiest way of writing the constraints for FMC I/O pins is making use of a script called adi_fmc_constr_generator.tcl.
Required setup:
Calling the script:
To use this script you can source it in any tcl shell or simply call the adi_fmc_constr_generator.tcl with argument(s) <fmc_port>. But before sourcing or calling it, your current directory needs to be hdl/tree/master/projects/<project>/<carrier>
For example:
If sourced without argument(s) then you can simply call gen_fmc_constr <fmc_port>.
For example:
The generated file will appear in the current directory as fmc_constr.xdc (Xilinx board) or fmc_constr.tcl (Intel board). If ran from an open Vivado project, the generated file will be automatically added to the project.
You can ask questions at FPGA Reference Design EZ community.
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