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This version is outdated by a newer approved version.DiffThis version (21 Mar 2018 13:55) was approved by Istvan Csomortani.The Previously approved version (02 Feb 2018 15:13) is available.Diff

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Table of Contents

Porting ADI's HDL reference designs

In general, a given reference design for an FMC board is deployed to just a few carriers, although several FPGA boards are supported in ADI's HDL repository. The simple reason behind this practice is that it would create a tremendous maintenance workload, that would require a lot of human resources, and would increase the required time for testing. The general rule of thumb is to support a given project with a fairly popular carrier (e.g. ZC706 or A10SoC), which is powerful enough to showcase the board features and maximum performance. All the HDL projects were designed to maximize source code reuse, minimize maintainability and simplify portability. The result of these design goals is that porting a given project to another carrier is fairly simple if the user respects a couple of guidelines. The main scope of this wiki page is to discuss these guidelines and provide simple indications for users who wants to port a project to a non-supported carrier.

Quick Compatibility Check

All ADI's FPGA Mezzanine Cards (FMC) are designed to respect all the specifications and requirements defined in the ANSI/VITA 57.1 FPGA Mezzanine Card Standard (if not otherwise stated on board's wiki page). If the new FPGA carrier is fully compliant with this standard, there will be no obstacles preventing the user to port the project to the required carrier card.

There are two types of FMC connector: LPC (Low Pin Count) and HPC (High Pin Count). In general, an FMC board is using the FMC connector type that has enough pins for the required interfaces between the IO devices and FPGA. A carrier with an FMC HPC connector can host FMC boards with an LPC or HPC connector, but a carrier with an FMC LPC can host a board just with an FMC LPC connector.

First, always check out the already available base designs. If your board is present among our supported base designs, you do not need to verify the following things and can jump to the Project creation section

The most important things to check before porting are related to the ANSI/VITA 57.1 standard (the list is not necessarily exhaustive):

  • Power and ground lines - 3P3V/3P3VAUX/12P0V/GND
  • VADJ - adjustable voltage level power from the carrier, each board has a specific requirement for VADJ
  • Dedicated pins for clock signals - all the clock dedicated pins should be connected to a clock capable pin of the FPGA (IO pin which is capable to receive and/or transmit a clock signal)
  • Dedicated pins for transceiver lines (DPx_[M2C|C2M]_[P|N])
To check all the requirements please refer to the ANSI/VITA 57.1 standard. The above few hints do not cover all the FMC standard and you may miss something that can prevent the port of the project.
Make sure that you've reviewed all the documentation and design files in order to know the electrical specifications and/or requirements of the FMC board. If you're not sure, ask!

Base design files

At HDL Architecture wiki describes a generic base design and possible components of it. The user should look at it as a suggestion only.

Example with a Xilinx board

In this section, we are presenting all the necessary steps to create a base design for the Xilinx ZCU102 development board.

First, you need to create a new directory in ~/projects/common with the name of the carrier. 

[~/hdl]cd projects/common
[~/hdl]mkdir zcu102

The zcu102 directory must contain the following files:

  • zcu102_system_bd.tcl - This script describes the base block design
  • zcu102_system_constr.xdc - IO constraint file for the base design. Will contain IO definitions for GPIO, switches, LEDs or other peripherals of the board
  • MIG configuration file (if needed) - This file can be borrowed for the golden reference design of the board
  • other constraints files if needed

You should define the board and its device in the project flow script, called (adi_project.tcl), by adding the following lines to the beginning of the adi_project_create process: 

if [regexp "_zcu102$" $project_name] {
    set p_device "xczu9eg-ffvb1156-1-i-es1"
    set p_board "xilinx.com:zcu102:part0:1.2"
    set sys_zynq 2
}
The valid board parts and parts can be retrieved by running the following commands in Tcl console: get_parts and get_board_parts. Run the commands like join [get_parts] \n, so each part name will be listed on a separate line.

The sys_zynq constant variable should be set in the following way:

  • 0 - 7 Series FPGA (e.g. Kintex7, Virtex7)
  • 1 - Zynq7000 SoC
  • 2 - Zynq Ultrascale+ SoC

Example with an Intel board

To create a new base design for a given Intel FPGA carrier board the following steps should be taken (the a10soc carrier was used as an example).

The following files should be created or copied into the directory:

  • a10soc_system_assign.tcl - global and IO assignments of the base design
  • a10soc_system_qsys.tcl - the QSYS base design

You should define the board and its device in the flow script (adi_project_alt.tcl), by adding the following lines to the beginning of the adi_project_altera process: 

if [regexp "_a10soc$" $project_name] {
    set family "Arria 10"
    set device 10AS066N3F40E2SG
    set system_qip_file system_bd/system_bd.qip
}

Project files for Xilinx boards

To follow the project framework as much as possible the easiest way is to copy all the projects files from an already existing project and modifying those file to support the new carrier. A project for a Xilinx FPGA board should contain the following files:

  • system_project.tcl - This script is creating the actual Vivado project and runs the synthesis/implementation of the design. The name of the carrier must be updated.
  • system_bd.tcl - In this file is sourced the base design's Tcl script and the board design's Tcl script. The name of the carrier must be updated.
  • system_constr.xdc - Constraint files of the board design. Here is defined the FMC IO's and board specific clock signals. All the IO definition must be updated, with the new pin names.
  • system_top.v - Top wrapper file, in which the system_wrapper.v module is instantiated, and a few I/O macros are defined. The IO port of this Verilog module will be connected to actual IO pads of the FPGA. The simplest way to update the system_top is to let the synthesis fail and the tool will tell which ports are missing or which ports are redundant. The first thing to do after the failure is to verify the instantiation of the system_wrapper.v. This file is a tool generated file and can be found at <project_name>.srcs/sources_1/bd/system/hdl/system_wrapper.v. Fixing the instantiation of the wrapper module in most cases eliminates all the errors. If you get errors that you can not fix, ask for support.
  • Makefile - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue.

Project files for Intel boards

To follow the project framework as much as possible the easiest way is to copy all the projects file from an already existing project and modifying those files to support the new carrier. A project for an Intel FPGA board should contain the following files:

  • system_project.tcl - This script is creating the actual Quartus project and run the synthesis/implementation of the design. It also contains the IO definitions for the interfaces between the FMC board and FPGA. The carrier name and all the IO pin names must be updated.
  • system_qsys.tcl - In this file is sourced the base design's Tcl script and the board design's Tcl script. The name of the carrier must be updated.
  • system_constr.sdc - Contains clock definitions and other path constraints
  • system_top.v - Top wrapper file of the project. The IO port of this Verilog module will be actual IO pads of the FPGA. Need to make sure that the base design's IOs are updated. (Delete nonexistent IO or add new ones). The simplest way to update the system_top is to let the synthesis fail and the tool will tell which ports are missing or which ports are redundant.
  • Makefile - This is an auto-generated file, but after updating the carrier name, it should work with the new project without an issue.

Help and support

You can ask questions at FPGA Reference Design EZ community.

Threads that discuss this issue:

References

resources/fpga/docs/hdl/porting_project_quick_start_guide.1521636911.txt.gz · Last modified: 21 Mar 2018 13:55 by Istvan Csomortani

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